#include "llvm/Function.h"
#include "llvm/GlobalVariable.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/DebugLoc.h"
#include "llvm/CodeGen/DwarfWriter.h"
#include "llvm/Analysis/DebugInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "SelectionDAGBuild.h"
using namespace llvm;
unsigned FastISel::getRegForValue(Value *V) {
MVT RealVT = TLI.getValueType(V->getType(), true);
if (!RealVT.isSimple())
return 0;
MVT::SimpleValueType VT = RealVT.getSimpleVT();
if (!TLI.isTypeLegal(VT)) {
if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
else
return 0;
}
if (ValueMap.count(V))
return ValueMap[V];
unsigned Reg = LocalValueMap[V];
if (Reg != 0)
return Reg;
if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
if (CI->getValue().getActiveBits() <= 64)
Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
} else if (isa<AllocaInst>(V)) {
Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
} else if (isa<ConstantPointerNull>(V)) {
Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
if (!Reg) {
const APFloat &Flt = CF->getValueAPF();
MVT IntVT = TLI.getPointerTy();
uint64_t x[2];
uint32_t IntBitWidth = IntVT.getSizeInBits();
bool isExact;
(void) Flt.convertToInteger(x, IntBitWidth, true,
APFloat::rmTowardZero, &isExact);
if (isExact) {
APInt IntVal(IntBitWidth, 2, x);
unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
if (IntegerReg != 0)
Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
}
}
} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
if (!SelectOperator(CE, CE->getOpcode())) return 0;
Reg = LocalValueMap[CE];
} else if (isa<UndefValue>(V)) {
Reg = createResultReg(TLI.getRegClassFor(VT));
BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
}
if (!Reg && isa<Constant>(V))
Reg = TargetMaterializeConstant(cast<Constant>(V));
if (Reg != 0)
LocalValueMap[V] = Reg;
return Reg;
}
unsigned FastISel::lookUpRegForValue(Value *V) {
if (ValueMap.count(V))
return ValueMap[V];
return LocalValueMap[V];
}
unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
if (!isa<Instruction>(I)) {
LocalValueMap[I] = Reg;
return Reg;
}
unsigned &AssignedReg = ValueMap[I];
if (AssignedReg == 0)
AssignedReg = Reg;
else if (Reg != AssignedReg) {
const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
Reg, RegClass, RegClass);
}
return AssignedReg;
}
unsigned FastISel::getRegForGEPIndex(Value *Idx) {
unsigned IdxN = getRegForValue(Idx);
if (IdxN == 0)
return 0;
MVT PtrVT = TLI.getPointerTy();
MVT IdxVT = MVT::getMVT(Idx->getType(), false);
if (IdxVT.bitsLT(PtrVT))
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
ISD::SIGN_EXTEND, IdxN);
else if (IdxVT.bitsGT(PtrVT))
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
ISD::TRUNCATE, IdxN);
return IdxN;
}
bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
MVT VT = MVT::getMVT(I->getType(), true);
if (VT == MVT::Other || !VT.isSimple())
return false;
if (!TLI.isTypeLegal(VT)) {
if (VT == MVT::i1 &&
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
ISDOpcode == ISD::XOR))
VT = TLI.getTypeToTransformTo(VT);
else
return false;
}
unsigned Op0 = getRegForValue(I->getOperand(0));
if (Op0 == 0)
return false;
if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
ISDOpcode, Op0, CI->getZExtValue());
if (ResultReg != 0) {
UpdateValueMap(I, ResultReg);
return true;
}
}
if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
ISDOpcode, Op0, CF);
if (ResultReg != 0) {
UpdateValueMap(I, ResultReg);
return true;
}
}
unsigned Op1 = getRegForValue(I->getOperand(1));
if (Op1 == 0)
return false;
unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
ISDOpcode, Op0, Op1);
if (ResultReg == 0)
return false;
UpdateValueMap(I, ResultReg);
return true;
}
bool FastISel::SelectGetElementPtr(User *I) {
unsigned N = getRegForValue(I->getOperand(0));
if (N == 0)
return false;
const Type *Ty = I->getOperand(0)->getType();
MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
OI != E; ++OI) {
Value *Idx = *OI;
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
if (Field) {
uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
if (N == 0)
return false;
}
Ty = StTy->getElementType(Field);
} else {
Ty = cast<SequentialType>(Ty)->getElementType();
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
if (CI->getZExtValue() == 0) continue;
uint64_t Offs =
TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
if (N == 0)
return false;
continue;
}
uint64_t ElementSize = TD.getTypePaddedSize(Ty);
unsigned IdxN = getRegForGEPIndex(Idx);
if (IdxN == 0)
return false;
if (ElementSize != 1) {
IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
if (IdxN == 0)
return false;
}
N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
if (N == 0)
return false;
}
}
UpdateValueMap(I, N);
return true;
}
bool FastISel::SelectCall(User *I) {
Function *F = cast<CallInst>(I)->getCalledFunction();
if (!F) return false;
unsigned IID = F->getIntrinsicID();
switch (IID) {
default: break;
case Intrinsic::dbg_stoppoint: {
DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
unsigned Line = SPI->getLine();
unsigned Col = SPI->getColumn();
unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col);
setCurDebugLoc(DebugLoc::get(Idx));
}
return true;
}
case Intrinsic::dbg_region_start: {
DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) &&
DW && DW->ShouldEmitDwarfDebug()) {
unsigned ID =
DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
BuildMI(MBB, DL, II).addImm(ID);
}
return true;
}
case Intrinsic::dbg_region_end: {
DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) &&
DW && DW->ShouldEmitDwarfDebug()) {
unsigned ID = 0;
DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
ID = DW->RecordInlinedFnEnd(Subprogram);
if (ID)
BuildMI(MBB, DL, II).addImm(ID);
} else {
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
BuildMI(MBB, DL, II).addImm(ID);
}
}
return true;
}
case Intrinsic::dbg_func_start: {
DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
Value *SP = FSI->getSubprogram();
if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None))
return true;
DebugLoc PrevLoc = DL;
DISubprogram Subprogram(cast<GlobalVariable>(SP));
DICompileUnit CompileUnit = Subprogram.getCompileUnit();
if (!Subprogram.describes(MF.getFunction())) {
if (PrevLoc.isUnknown())
return true;
unsigned Line = Subprogram.getLineNumber();
setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
CompileUnit.getGV(), Line, 0)));
if (DW && DW->ShouldEmitDwarfDebug()) {
DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
unsigned LabelID = DW->RecordInlinedFnStart(Subprogram,
DICompileUnit(PrevLocTpl.CompileUnit),
PrevLocTpl.Line,
PrevLocTpl.Col);
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
BuildMI(MBB, DL, II).addImm(LabelID);
}
} else {
unsigned Line = Subprogram.getLineNumber();
MF.setDefaultDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
CompileUnit.getGV(), Line, 0)));
if (DW && DW->ShouldEmitDwarfDebug()) {
DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
}
}
return true;
}
case Intrinsic::dbg_declare: {
DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
Value *Variable = DI->getVariable();
if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) &&
DW && DW->ShouldEmitDwarfDebug()) {
Value *Address = DI->getAddress();
if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
Address = BCI->getOperand(0);
AllocaInst *AI = dyn_cast<AllocaInst>(Address);
if (!AI) break;
DenseMap<const AllocaInst*, int>::iterator SI =
StaticAllocaMap.find(AI);
if (SI == StaticAllocaMap.end()) break; int FI = SI->second;
GlobalValue *GV = cast<GlobalVariable>(Variable);
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
MachineInstr *DeclareMI
= BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
DIVariable DV(cast<GlobalVariable>(GV));
if (!DV.isNull()) {
DW->RecordVariableScope(DV, DeclareMI);
}
}
return true;
}
case Intrinsic::eh_exception: {
MVT VT = TLI.getValueType(I->getType());
switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
default: break;
case TargetLowering::Expand: {
if (!MBB->isLandingPad()) {
unsigned Reg = TLI.getExceptionAddressRegister();
if (Reg) MBB->addLiveIn(Reg);
}
unsigned Reg = TLI.getExceptionAddressRegister();
const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
unsigned ResultReg = createResultReg(RC);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
Reg, RC, RC);
assert(InsertedCopy && "Can't copy address registers!");
InsertedCopy = InsertedCopy;
UpdateValueMap(I, ResultReg);
return true;
}
}
break;
}
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
MVT VT = TLI.getValueType(I->getType());
switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
default: break;
case TargetLowering::Expand: {
MVT VT = (IID == Intrinsic::eh_selector_i32 ?
MVT::i32 : MVT::i64);
if (MMI) {
if (MBB->isLandingPad())
AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
else {
#ifndef NDEBUG
CatchInfoLost.insert(cast<CallInst>(I));
#endif
unsigned Reg = TLI.getExceptionSelectorRegister();
if (Reg) MBB->addLiveIn(Reg);
}
unsigned Reg = TLI.getExceptionSelectorRegister();
const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
unsigned ResultReg = createResultReg(RC);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
Reg, RC, RC);
assert(InsertedCopy && "Can't copy address registers!");
InsertedCopy = InsertedCopy;
UpdateValueMap(I, ResultReg);
} else {
unsigned ResultReg =
getRegForValue(Constant::getNullValue(I->getType()));
UpdateValueMap(I, ResultReg);
}
return true;
}
}
break;
}
}
return false;
}
bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
MVT DstVT = TLI.getValueType(I->getType());
if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
DstVT == MVT::Other || !DstVT.isSimple())
return false;
if (!TLI.isTypeLegal(DstVT))
if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
return false;
if (!TLI.isTypeLegal(SrcVT))
if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
return false;
unsigned InputReg = getRegForValue(I->getOperand(0));
if (!InputReg)
return false;
if (SrcVT == MVT::i1) {
SrcVT = TLI.getTypeToTransformTo(SrcVT);
InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
if (!InputReg)
return false;
}
if (DstVT == MVT::i1)
DstVT = TLI.getTypeToTransformTo(DstVT);
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
DstVT.getSimpleVT(),
Opcode,
InputReg);
if (!ResultReg)
return false;
UpdateValueMap(I, ResultReg);
return true;
}
bool FastISel::SelectBitCast(User *I) {
if (I->getType() == I->getOperand(0)->getType()) {
unsigned Reg = getRegForValue(I->getOperand(0));
if (Reg == 0)
return false;
UpdateValueMap(I, Reg);
return true;
}
MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
MVT DstVT = TLI.getValueType(I->getType());
if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
DstVT == MVT::Other || !DstVT.isSimple() ||
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
return false;
unsigned Op0 = getRegForValue(I->getOperand(0));
if (Op0 == 0)
return false;
unsigned ResultReg = 0;
if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
ResultReg = createResultReg(DstClass);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
Op0, DstClass, SrcClass);
if (!InsertedCopy)
ResultReg = 0;
}
if (!ResultReg)
ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
ISD::BIT_CONVERT, Op0);
if (!ResultReg)
return false;
UpdateValueMap(I, ResultReg);
return true;
}
bool
FastISel::SelectInstruction(Instruction *I) {
return SelectOperator(I, I->getOpcode());
}
void
FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
MachineFunction::iterator NextMBB =
next(MachineFunction::iterator(MBB));
if (MBB->isLayoutSuccessor(MSucc)) {
} else {
TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
}
MBB->addSuccessor(MSucc);
}
bool
FastISel::SelectOperator(User *I, unsigned Opcode) {
switch (Opcode) {
case Instruction::Add: {
ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
return SelectBinaryOp(I, Opc);
}
case Instruction::Sub: {
ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
return SelectBinaryOp(I, Opc);
}
case Instruction::Mul: {
ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
return SelectBinaryOp(I, Opc);
}
case Instruction::SDiv:
return SelectBinaryOp(I, ISD::SDIV);
case Instruction::UDiv:
return SelectBinaryOp(I, ISD::UDIV);
case Instruction::FDiv:
return SelectBinaryOp(I, ISD::FDIV);
case Instruction::SRem:
return SelectBinaryOp(I, ISD::SREM);
case Instruction::URem:
return SelectBinaryOp(I, ISD::UREM);
case Instruction::FRem:
return SelectBinaryOp(I, ISD::FREM);
case Instruction::Shl:
return SelectBinaryOp(I, ISD::SHL);
case Instruction::LShr:
return SelectBinaryOp(I, ISD::SRL);
case Instruction::AShr:
return SelectBinaryOp(I, ISD::SRA);
case Instruction::And:
return SelectBinaryOp(I, ISD::AND);
case Instruction::Or:
return SelectBinaryOp(I, ISD::OR);
case Instruction::Xor:
return SelectBinaryOp(I, ISD::XOR);
case Instruction::GetElementPtr:
return SelectGetElementPtr(I);
case Instruction::Br: {
BranchInst *BI = cast<BranchInst>(I);
if (BI->isUnconditional()) {
BasicBlock *LLVMSucc = BI->getSuccessor(0);
MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
FastEmitBranch(MSucc);
return true;
}
return false;
}
case Instruction::Unreachable:
return true;
case Instruction::PHI:
return true;
case Instruction::Alloca:
if (StaticAllocaMap.count(cast<AllocaInst>(I)))
return true;
return false;
case Instruction::Call:
return SelectCall(I);
case Instruction::BitCast:
return SelectBitCast(I);
case Instruction::FPToSI:
return SelectCast(I, ISD::FP_TO_SINT);
case Instruction::ZExt:
return SelectCast(I, ISD::ZERO_EXTEND);
case Instruction::SExt:
return SelectCast(I, ISD::SIGN_EXTEND);
case Instruction::Trunc:
return SelectCast(I, ISD::TRUNCATE);
case Instruction::SIToFP:
return SelectCast(I, ISD::SINT_TO_FP);
case Instruction::IntToPtr: case Instruction::PtrToInt: {
MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
MVT DstVT = TLI.getValueType(I->getType());
if (DstVT.bitsGT(SrcVT))
return SelectCast(I, ISD::ZERO_EXTEND);
if (DstVT.bitsLT(SrcVT))
return SelectCast(I, ISD::TRUNCATE);
unsigned Reg = getRegForValue(I->getOperand(0));
if (Reg == 0) return false;
UpdateValueMap(I, Reg);
return true;
}
default:
return false;
}
}
FastISel::FastISel(MachineFunction &mf,
MachineModuleInfo *mmi,
DwarfWriter *dw,
DenseMap<const Value *, unsigned> &vm,
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
DenseMap<const AllocaInst *, int> &am
#ifndef NDEBUG
, SmallSet<Instruction*, 8> &cil
#endif
)
: MBB(0),
ValueMap(vm),
MBBMap(bm),
StaticAllocaMap(am),
#ifndef NDEBUG
CatchInfoLost(cil),
#endif
MF(mf),
MMI(mmi),
DW(dw),
MRI(MF.getRegInfo()),
MFI(*MF.getFrameInfo()),
MCP(*MF.getConstantPool()),
TM(MF.getTarget()),
TD(*TM.getTargetData()),
TII(*TM.getInstrInfo()),
TLI(*TM.getTargetLowering()) {
}
FastISel::~FastISel() {}
unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType) {
return 0;
}
unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType, unsigned ) {
return 0;
}
unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType, unsigned ,
unsigned ) {
return 0;
}
unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType, uint64_t ) {
return 0;
}
unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType, ConstantFP * ) {
return 0;
}
unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType, unsigned ,
uint64_t ) {
return 0;
}
unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType, unsigned ,
ConstantFP * ) {
return 0;
}
unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType,
unsigned , unsigned ,
uint64_t ) {
return 0;
}
unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
MVT::SimpleValueType ImmType) {
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
if (ResultReg != 0)
return ResultReg;
unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
if (MaterialReg == 0)
return 0;
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
}
unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
MVT::SimpleValueType ImmType) {
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
if (ResultReg != 0)
return ResultReg;
unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
if (MaterialReg == 0) {
const APFloat &Flt = FPImm->getValueAPF();
MVT IntVT = TLI.getPointerTy();
uint64_t x[2];
uint32_t IntBitWidth = IntVT.getSizeInBits();
bool isExact;
(void) Flt.convertToInteger(x, IntBitWidth, true,
APFloat::rmTowardZero, &isExact);
if (!isExact)
return 0;
APInt IntVal(IntBitWidth, 2, x);
unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
ISD::Constant, IntVal.getZExtValue());
if (IntegerReg == 0)
return 0;
MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
ISD::SINT_TO_FP, IntegerReg);
if (MaterialReg == 0)
return 0;
}
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
}
unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
return MRI.createVirtualRegister(RC);
}
unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
const TargetRegisterClass* RC) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
BuildMI(MBB, DL, II, ResultReg);
return ResultReg;
}
unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
if (II.getNumDefs() >= 1)
BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
else {
BuildMI(MBB, DL, II).addReg(Op0);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
II.ImplicitDefs[0], RC, RC);
if (!InsertedCopy)
ResultReg = 0;
}
return ResultReg;
}
unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
if (II.getNumDefs() >= 1)
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
else {
BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
II.ImplicitDefs[0], RC, RC);
if (!InsertedCopy)
ResultReg = 0;
}
return ResultReg;
}
unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, uint64_t Imm) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
if (II.getNumDefs() >= 1)
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
else {
BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
II.ImplicitDefs[0], RC, RC);
if (!InsertedCopy)
ResultReg = 0;
}
return ResultReg;
}
unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, ConstantFP *FPImm) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
if (II.getNumDefs() >= 1)
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
else {
BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
II.ImplicitDefs[0], RC, RC);
if (!InsertedCopy)
ResultReg = 0;
}
return ResultReg;
}
unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1, uint64_t Imm) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
if (II.getNumDefs() >= 1)
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
else {
BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
II.ImplicitDefs[0], RC, RC);
if (!InsertedCopy)
ResultReg = 0;
}
return ResultReg;
}
unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
uint64_t Imm) {
unsigned ResultReg = createResultReg(RC);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
if (II.getNumDefs() >= 1)
BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
else {
BuildMI(MBB, DL, II).addImm(Imm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
II.ImplicitDefs[0], RC, RC);
if (!InsertedCopy)
ResultReg = 0;
}
return ResultReg;
}
unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx) {
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
if (II.getNumDefs() >= 1)
BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
else {
BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
II.ImplicitDefs[0], RC, RC);
if (!InsertedCopy)
ResultReg = 0;
}
return ResultReg;
}
unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
}