LiveIntervalAnalysis.h [plain text]
#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Allocator.h"
#include <cmath>
namespace llvm {
class AliasAnalysis;
class LiveVariables;
class MachineLoopInfo;
class TargetRegisterInfo;
class MachineRegisterInfo;
class TargetInstrInfo;
class TargetRegisterClass;
class VirtRegMap;
typedef std::pair<unsigned, MachineBasicBlock*> IdxMBBPair;
inline bool operator<(unsigned V, const IdxMBBPair &IM) {
return V < IM.first;
}
inline bool operator<(const IdxMBBPair &IM, unsigned V) {
return IM.first < V;
}
struct Idx2MBBCompare {
bool operator()(const IdxMBBPair &LHS, const IdxMBBPair &RHS) const {
return LHS.first < RHS.first;
}
};
class LiveIntervals : public MachineFunctionPass {
MachineFunction* mf_;
MachineRegisterInfo* mri_;
const TargetMachine* tm_;
const TargetRegisterInfo* tri_;
const TargetInstrInfo* tii_;
AliasAnalysis *aa_;
LiveVariables* lv_;
BumpPtrAllocator VNInfoAllocator;
std::vector<std::pair<unsigned, unsigned> > MBB2IdxMap;
std::vector<IdxMBBPair> Idx2MBBMap;
uint64_t FunctionSize;
typedef DenseMap<MachineInstr*, unsigned> Mi2IndexMap;
Mi2IndexMap mi2iMap_;
typedef std::vector<MachineInstr*> Index2MiMap;
Index2MiMap i2miMap_;
typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
Reg2IntervalMap r2iMap_;
BitVector allocatableRegs_;
std::vector<MachineInstr*> ClonedMIs;
public:
static char ID; LiveIntervals() : MachineFunctionPass(&ID) {}
struct InstrSlots {
enum {
LOAD = 0,
USE = 1,
DEF = 2,
STORE = 3,
NUM = 4
};
};
static unsigned getBaseIndex(unsigned index) {
return index - (index % InstrSlots::NUM);
}
static unsigned getBoundaryIndex(unsigned index) {
return getBaseIndex(index + InstrSlots::NUM - 1);
}
static unsigned getLoadIndex(unsigned index) {
return getBaseIndex(index) + InstrSlots::LOAD;
}
static unsigned getUseIndex(unsigned index) {
return getBaseIndex(index) + InstrSlots::USE;
}
static unsigned getDefIndex(unsigned index) {
return getBaseIndex(index) + InstrSlots::DEF;
}
static unsigned getStoreIndex(unsigned index) {
return getBaseIndex(index) + InstrSlots::STORE;
}
static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
return (isDef + isUse) * powf(10.0F, (float)loopDepth);
}
typedef Reg2IntervalMap::iterator iterator;
typedef Reg2IntervalMap::const_iterator const_iterator;
const_iterator begin() const { return r2iMap_.begin(); }
const_iterator end() const { return r2iMap_.end(); }
iterator begin() { return r2iMap_.begin(); }
iterator end() { return r2iMap_.end(); }
unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
LiveInterval &getInterval(unsigned reg) {
Reg2IntervalMap::iterator I = r2iMap_.find(reg);
assert(I != r2iMap_.end() && "Interval does not exist for register");
return *I->second;
}
const LiveInterval &getInterval(unsigned reg) const {
Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
assert(I != r2iMap_.end() && "Interval does not exist for register");
return *I->second;
}
bool hasInterval(unsigned reg) const {
return r2iMap_.count(reg);
}
unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
return getMBBStartIdx(MBB->getNumber());
}
unsigned getMBBStartIdx(unsigned MBBNo) const {
assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
return MBB2IdxMap[MBBNo].first;
}
unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
return getMBBEndIdx(MBB->getNumber());
}
unsigned getMBBEndIdx(unsigned MBBNo) const {
assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
return MBB2IdxMap[MBBNo].second;
}
double getScaledIntervalSize(LiveInterval& I) {
return (1000.0 / InstrSlots::NUM * I.getSize()) / i2miMap_.size();
}
unsigned getApproximateInstructionCount(LiveInterval& I) {
double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
return (unsigned)(IntervalPercentage * FunctionSize);
}
MachineBasicBlock* getMBBFromIndex(unsigned index) const {
std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), index);
std::vector<IdxMBBPair>::const_iterator J =
((I != Idx2MBBMap.end() && I->first > index) ||
(I == Idx2MBBMap.end() && Idx2MBBMap.size()>0)) ? (I-1): I;
assert(J != Idx2MBBMap.end() && J->first < index+1 &&
index <= getMBBEndIdx(J->second) &&
"index does not correspond to an MBB");
return J->second;
}
unsigned getInstructionIndex(MachineInstr* instr) const {
Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
assert(it != mi2iMap_.end() && "Invalid instruction!");
return it->second;
}
MachineInstr* getInstructionFromIndex(unsigned index) const {
index /= InstrSlots::NUM; assert(index < i2miMap_.size() &&
"index does not correspond to an instruction");
return i2miMap_[index];
}
bool hasGapBeforeInstr(unsigned Index) {
Index = getBaseIndex(Index - InstrSlots::NUM);
return getInstructionFromIndex(Index) == 0;
}
unsigned findGapBeforeInstr(unsigned Index, bool Furthest = false) {
Index = getBaseIndex(Index - InstrSlots::NUM);
if (getInstructionFromIndex(Index))
return 0; if (!Furthest)
return Index;
unsigned PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
while (getInstructionFromIndex(Index)) {
Index = PrevIndex;
PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
}
return Index;
}
void InsertMachineInstrInMaps(MachineInstr *MI, unsigned Index) {
i2miMap_[Index / InstrSlots::NUM] = MI;
Mi2IndexMap::iterator it = mi2iMap_.find(MI);
assert(it == mi2iMap_.end() && "Already in map!");
mi2iMap_[MI] = Index;
}
bool conflictsWithPhysRegDef(const LiveInterval &li, VirtRegMap &vrm,
unsigned reg);
bool conflictsWithPhysRegRef(LiveInterval &li, unsigned Reg,
bool CheckUse,
SmallPtrSet<MachineInstr*,32> &JoinedCopies);
bool findLiveInMBBs(unsigned Start, unsigned End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
bool findReachableMBBs(unsigned Start, unsigned End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
LiveInterval &getOrCreateInterval(unsigned reg) {
Reg2IntervalMap::iterator I = r2iMap_.find(reg);
if (I == r2iMap_.end())
I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
return *I->second;
}
LiveInterval *dupInterval(LiveInterval *li);
LiveRange addLiveRangeToEndOfBlock(unsigned reg,
MachineInstr* startInst);
void removeInterval(unsigned Reg) {
DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
delete I->second;
r2iMap_.erase(I);
}
bool isNotInMIMap(MachineInstr* instr) const {
return !mi2iMap_.count(instr);
}
void RemoveMachineInstrFromMaps(MachineInstr *MI) {
Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
if (mi2i != mi2iMap_.end()) {
i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
mi2iMap_.erase(mi2i);
}
}
void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
if (mi2i == mi2iMap_.end())
return;
i2miMap_[mi2i->second/InstrSlots::NUM] = NewMI;
Mi2IndexMap::iterator it = mi2iMap_.find(MI);
assert(it != mi2iMap_.end() && "Invalid instruction!");
unsigned Index = it->second;
mi2iMap_.erase(it);
mi2iMap_[NewMI] = Index;
}
BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual void releaseMemory();
virtual bool runOnMachineFunction(MachineFunction&);
virtual void print(std::ostream &O, const Module* = 0) const;
void print(std::ostream *O, const Module* M = 0) const {
if (O) print(*O, M);
}
std::vector<LiveInterval*>
addIntervalsForSpills(const LiveInterval& i,
SmallVectorImpl<LiveInterval*> &SpillIs,
const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
std::vector<LiveInterval*>
addIntervalsForSpillsFast(const LiveInterval &li,
const MachineLoopInfo *loopInfo, VirtRegMap &vrm);
bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
unsigned PhysReg, VirtRegMap &vrm);
bool isReMaterializable(const LiveInterval &li,
SmallVectorImpl<LiveInterval*> &SpillIs,
bool &isLoad);
bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
MachineInstr *MI);
unsigned getRepresentativeReg(unsigned Reg) const;
unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
unsigned PhysReg) const;
void computeNumbering();
bool intervalIsInOneMBB(const LiveInterval &li) const;
private:
void computeIntervals();
void handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI, unsigned MIIdx,
MachineOperand& MO, unsigned MOIdx);
void handleVirtualRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
unsigned MIIdx, MachineOperand& MO,
unsigned MOIdx, LiveInterval& interval);
void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
MachineBasicBlock::iterator mi,
unsigned MIIdx, MachineOperand& MO,
LiveInterval &interval,
MachineInstr *CopyMI);
void handleLiveInRegister(MachineBasicBlock* mbb,
unsigned MIIdx,
LiveInterval &interval, bool isAlias = false);
unsigned getReMatImplicitUse(const LiveInterval &li,
MachineInstr *MI) const;
bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
unsigned UseIdx) const;
bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
MachineInstr *MI,
SmallVectorImpl<LiveInterval*> &SpillIs,
bool &isLoad);
bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
MachineInstr *DefMI, unsigned InstrIdx,
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg);
bool canFoldMemoryOperand(MachineInstr *MI,
SmallVector<unsigned, 2> &Ops,
bool ReMatLoadSS) const;
bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
MachineBasicBlock *MBB, unsigned Idx) const;
bool hasAllocatableSuperReg(unsigned Reg) const;
struct SRInfo {
int index;
unsigned vreg;
bool canFold;
SRInfo(int i, unsigned vr, bool f) : index(i), vreg(vr), canFold(f) {};
};
bool alsoFoldARestore(int Id, int index, unsigned vr,
BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
void eraseRestoreInfo(int Id, int index, unsigned vr,
BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
const TargetRegisterClass* rc,
std::vector<LiveInterval*> &NewLIs);
void rewriteImplicitOps(const LiveInterval &li,
MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
VirtRegMap &vrm, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs);
void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
LiveInterval::Ranges::const_iterator &I,
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
VirtRegMap &vrm, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs,
DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs,
DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs);
static LiveInterval* createInterval(unsigned Reg);
void printRegName(unsigned reg) const;
};
}
#endif