MachineRegisterInfo.cpp [plain text]
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()];
UsedPhysRegs.resize(TRI.getNumRegs());
PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
}
MachineRegisterInfo::~MachineRegisterInfo() {
#ifndef NDEBUG
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
"Vreg use list non-empty still?");
for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
assert(!PhysRegUseDefLists[i] &&
"PhysRegUseDefLists has entries after all instructions are deleted");
#endif
delete [] PhysRegUseDefLists;
delete [] RegClass2VRegMap;
}
void
MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
VRegInfo[Reg].first = RC;
std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
std::vector<unsigned>::iterator I =
std::find(VRegs.begin(), VRegs.end(), Reg);
VRegs.erase(I);
RegClass2VRegMap[RC->getID()].push_back(Reg);
}
const TargetRegisterClass *
MachineRegisterInfo::constrainRegClass(unsigned Reg,
const TargetRegisterClass *RC) {
const TargetRegisterClass *OldRC = getRegClass(Reg);
if (OldRC == RC)
return RC;
const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
if (!NewRC)
return 0;
if (NewRC != OldRC)
setRegClass(Reg, NewRC);
return NewRC;
}
unsigned
MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
assert(RegClass && "Cannot create register without RegClass!");
unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
VRegInfo.grow(Reg);
VRegInfo[Reg].first = RegClass;
RegAllocHints.grow(Reg);
if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
HandleVRegListReallocation();
RegClass2VRegMap[RegClass->getID()].push_back(Reg);
return Reg;
}
void MachineRegisterInfo::HandleVRegListReallocation() {
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
MachineOperand *List = VRegInfo[Reg].second;
if (!List) continue;
List->Contents.Reg.Prev = &VRegInfo[Reg].second;
}
}
void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
assert(FromReg != ToReg && "Cannot replace a reg with itself");
for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
MachineOperand &O = I.getOperand();
++I;
O.setReg(ToReg);
}
}
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
if (!def_empty(Reg))
return &*def_begin(Reg);
return 0;
}
bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
use_iterator UI = use_begin(RegNo);
if (UI == use_end())
return false;
return ++UI == use_end();
}
bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
use_nodbg_iterator UI = use_nodbg_begin(RegNo);
if (UI == use_nodbg_end())
return false;
return ++UI == use_nodbg_end();
}
void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
UI.getOperand().setIsKill(false);
}
bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
if (I->first == Reg || I->second == Reg)
return true;
return false;
}
bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
if (*I == Reg)
return true;
return false;
}
unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
if (I->second == VReg)
return I->first;
return 0;
}
unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
if (I->first == PReg)
return I->second;
return 0;
}
void
MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII) {
for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
if (LiveIns[i].second) {
if (use_empty(LiveIns[i].second)) {
LiveIns.erase(LiveIns.begin() + i);
--i; --e;
} else {
BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
TII.get(TargetOpcode::COPY), LiveIns[i].second)
.addReg(LiveIns[i].first);
EntryMBB->addLiveIn(LiveIns[i].first);
}
} else {
EntryMBB->addLiveIn(LiveIns[i].first);
}
}
void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
for (int i = UsedPhysRegs.find_first(); i >= 0;
i = UsedPhysRegs.find_next(i))
for (const unsigned *SS = TRI.getSubRegisters(i);
unsigned SubReg = *SS; ++SS)
if (SubReg > unsigned(i))
UsedPhysRegs.set(SubReg);
}
#ifndef NDEBUG
void MachineRegisterInfo::dumpUses(unsigned Reg) const {
for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
I.getOperand().getParent()->dump();
}
#endif