LiveIntervalUnion.cpp [plain text]
#define DEBUG_TYPE "regalloc"
#include "LiveIntervalUnion.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/CodeGen/MachineLoopRanges.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
if (VirtReg.empty())
return;
++Tag;
LiveInterval::iterator RegPos = VirtReg.begin();
LiveInterval::iterator RegEnd = VirtReg.end();
SegmentIter SegPos = Segments.find(RegPos->start);
while (SegPos.valid()) {
SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
if (++RegPos == RegEnd)
return;
SegPos.advanceTo(RegPos->start);
}
--RegEnd;
SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
for (; RegPos != RegEnd; ++RegPos, ++SegPos)
SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
}
void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
if (VirtReg.empty())
return;
++Tag;
LiveInterval::iterator RegPos = VirtReg.begin();
LiveInterval::iterator RegEnd = VirtReg.end();
SegmentIter SegPos = Segments.find(RegPos->start);
for (;;) {
assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
SegPos.erase();
if (!SegPos.valid())
return;
RegPos = VirtReg.advanceTo(RegPos, SegPos.start());
if (RegPos == RegEnd)
return;
SegPos.advanceTo(RegPos->start);
}
}
void
LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
OS << "LIU " << PrintReg(RepReg, TRI);
if (empty()) {
OS << " empty\n";
return;
}
for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
OS << " [" << SI.start() << ' ' << SI.stop() << "):"
<< PrintReg(SI.value()->reg, TRI);
}
OS << '\n';
}
void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
const TargetRegisterInfo *TRI) const {
OS << '[' << start() << ';' << stop() << "):"
<< PrintReg(interference()->reg, TRI);
}
void LiveIntervalUnion::Query::print(raw_ostream &OS,
const TargetRegisterInfo *TRI) {
OS << "Interferences with ";
LiveUnion->print(OS, TRI);
InterferenceResult IR = firstInterference();
while (isInterference(IR)) {
OS << " ";
IR.print(OS, TRI);
OS << '\n';
nextInterference(IR);
}
}
#ifndef NDEBUG
void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
VisitedVRegs.set(SI.value()->reg);
}
#endif //!NDEBUG
void LiveIntervalUnion::Query::findIntersection(InterferenceResult &IR) const {
LiveInterval::iterator VirtRegEnd = VirtReg->end();
if (IR.VirtRegI == VirtRegEnd)
return;
while (IR.LiveUnionI.valid()) {
IR.VirtRegI = VirtReg->advanceTo(IR.VirtRegI, IR.LiveUnionI.start());
if (IR.VirtRegI == VirtRegEnd)
break;
IR.LiveUnionI.advanceTo(IR.VirtRegI->start);
if (!IR.LiveUnionI.valid())
break;
if (IR.LiveUnionI.start() < IR.VirtRegI->end) {
assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
"upperBound postcondition");
break;
}
}
if (!IR.LiveUnionI.valid())
IR.VirtRegI = VirtRegEnd;
}
const LiveIntervalUnion::InterferenceResult &
LiveIntervalUnion::Query::firstInterference() {
if (CheckedFirstInterference)
return FirstInterference;
CheckedFirstInterference = true;
InterferenceResult &IR = FirstInterference;
IR.LiveUnionI.setMap(LiveUnion->getMap());
if (VirtReg->empty() || LiveUnion->empty()) {
IR.VirtRegI = VirtReg->end();
} else if (VirtReg->beginIndex() < LiveUnion->startIndex()) {
IR.VirtRegI = VirtReg->find(LiveUnion->startIndex());
if (IR.VirtRegI != VirtReg->end())
IR.LiveUnionI.find(IR.VirtRegI->start);
} else {
IR.LiveUnionI.find(VirtReg->beginIndex());
if (IR.LiveUnionI.valid())
IR.VirtRegI = VirtReg->find(IR.LiveUnionI.start());
else
IR.VirtRegI = VirtReg->end();
}
findIntersection(FirstInterference);
assert((IR.VirtRegI == VirtReg->end() || IR.LiveUnionI.valid())
&& "Uninitialized iterator");
return FirstInterference;
}
bool LiveIntervalUnion::Query::nextInterference(InterferenceResult &IR) const {
assert(isInterference(IR) && "iteration past end of interferences");
if (IR.VirtRegI->end < IR.LiveUnionI.stop()) {
if (++IR.VirtRegI == VirtReg->end())
return false;
}
else {
if (!(++IR.LiveUnionI).valid()) {
IR.VirtRegI = VirtReg->end();
return false;
}
}
if (overlap(*IR.VirtRegI, IR.LiveUnionI))
return true;
findIntersection(IR);
return isInterference(IR);
}
bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
SmallVectorImpl<LiveInterval*>::const_iterator I =
std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
return I != InterferingVRegs.end();
}
unsigned LiveIntervalUnion::Query::
collectInterferingVRegs(unsigned MaxInterferingRegs, float MaxWeight) {
InterferenceResult IR = firstInterference();
LiveInterval::iterator VirtRegEnd = VirtReg->end();
LiveInterval *RecentInterferingVReg = NULL;
if (IR.VirtRegI != VirtRegEnd) while (IR.LiveUnionI.valid()) {
do {
if (IR.LiveUnionI.value() == RecentInterferingVReg)
continue;
if (!isSeenInterference(IR.LiveUnionI.value()))
break;
RecentInterferingVReg = IR.LiveUnionI.value();
} while ((++IR.LiveUnionI).valid());
if (!IR.LiveUnionI.valid())
break;
IR.VirtRegI = VirtReg->advanceTo(IR.VirtRegI, IR.LiveUnionI.start());
if (IR.VirtRegI == VirtRegEnd)
break;
if (overlap(*IR.VirtRegI, IR.LiveUnionI)) {
if (!IR.LiveUnionI.value()->isSpillable())
SeenUnspillableVReg = true;
if (InterferingVRegs.size() == MaxInterferingRegs)
return MaxInterferingRegs;
InterferingVRegs.push_back(IR.LiveUnionI.value());
RecentInterferingVReg = IR.LiveUnionI.value();
++IR.LiveUnionI;
if (RecentInterferingVReg->weight >= MaxWeight)
return InterferingVRegs.size();
continue;
}
IR.LiveUnionI.advanceTo(IR.VirtRegI->start);
}
SeenAllInterferences = true;
return InterferingVRegs.size();
}
bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
IntervalMapOverlaps<LiveIntervalUnion::Map, MachineLoopRange::Map>
Overlaps(LiveUnion->getMap(), Loop->getMap());
if (!Overlaps.valid())
return false;
LiveInterval::iterator VRI = VirtReg->find(Overlaps.start());
for (;;) {
if (VRI == VirtReg->end())
return false;
if (VRI->start < Overlaps.stop())
return true;
Overlaps.advanceTo(VRI->start);
if (!Overlaps.valid())
return false;
if (Overlaps.start() < VRI->end)
return true;
VRI = VirtReg->advanceTo(VRI, Overlaps.start());
}
}