#define DEBUG_TYPE "subtarget"
#include "X86Subtarget.h"
#include "X86InstrInfo.h"
#include "X86GenSubtarget.inc"
#include "llvm/GlobalValue.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/System/Host.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/SmallVector.h"
using namespace llvm;
#if defined(_MSC_VER)
#include <intrin.h>
#endif
unsigned char X86Subtarget::
ClassifyBlockAddressReference() const {
if (isPICStyleGOT()) return X86II::MO_GOTOFF;
if (isPICStyleStubPIC()) return X86II::MO_PIC_BASE_OFFSET;
return X86II::MO_NO_FLAG;
}
unsigned char X86Subtarget::
ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
if (GV->hasDLLImportLinkage())
return X86II::MO_DLLIMPORT;
bool isDecl = GV->hasAvailableExternallyLinkage();
if (GV->isDeclaration() && !GV->isMaterializable())
isDecl = true;
if (isPICStyleRIPRel()) {
if (TM.getCodeModel() == CodeModel::Large)
return X86II::MO_NO_FLAG;
if (isTargetDarwin()) {
if (GV->hasDefaultVisibility() &&
(isDecl || GV->isWeakForLinker()))
return X86II::MO_GOTPCREL;
} else if (!isTargetWin64()) {
assert(isTargetELF() && "Unknown rip-relative target");
if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
return X86II::MO_GOTPCREL;
}
return X86II::MO_NO_FLAG;
}
if (isPICStyleGOT()) { if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
return X86II::MO_GOTOFF;
return X86II::MO_GOT;
}
if (isPICStyleStubPIC()) {
if (!isDecl && !GV->isWeakForLinker())
return X86II::MO_PIC_BASE_OFFSET;
if (!GV->hasHiddenVisibility()) return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
if (isDecl || GV->hasCommonLinkage()) {
return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
}
return X86II::MO_PIC_BASE_OFFSET;
}
if (isPICStyleStubNoDynamic()) {
if (!isDecl && !GV->isWeakForLinker())
return X86II::MO_NO_FLAG;
if (!GV->hasHiddenVisibility()) return X86II::MO_DARWIN_NONLAZY;
return X86II::MO_NO_FLAG;
}
return X86II::MO_NO_FLAG;
}
const char *X86Subtarget::getBZeroEntry() const {
if (getDarwinVers() >= 10)
return "__bzero";
return 0;
}
bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
if (Is64Bit)
return false;
return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
}
unsigned X86Subtarget::getSpecialAddressLatency() const {
return 200;
}
static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
#if defined(__GNUC__)
asm ("movq\t%%rbx, %%rsi\n\t"
"cpuid\n\t"
"xchgq\t%%rbx, %%rsi\n\t"
: "=a" (*rEAX),
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value));
return false;
#elif defined(_MSC_VER)
int registers[4];
__cpuid(registers, value);
*rEAX = registers[0];
*rEBX = registers[1];
*rECX = registers[2];
*rEDX = registers[3];
return false;
#endif
#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
#if defined(__GNUC__)
asm ("movl\t%%ebx, %%esi\n\t"
"cpuid\n\t"
"xchgl\t%%ebx, %%esi\n\t"
: "=a" (*rEAX),
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value));
return false;
#elif defined(_MSC_VER)
__asm {
mov eax,value
cpuid
mov esi,rEAX
mov dword ptr [esi],eax
mov esi,rEBX
mov dword ptr [esi],ebx
mov esi,rECX
mov dword ptr [esi],ecx
mov esi,rEDX
mov dword ptr [esi],edx
}
return false;
#endif
#endif
return true;
}
static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
Family = (EAX >> 8) & 0xf; Model = (EAX >> 4) & 0xf; if (Family == 6 || Family == 0xf) {
if (Family == 0xf)
Family += (EAX >> 20) & 0xff; Model += ((EAX >> 16) & 0xf) << 4; }
}
void X86Subtarget::AutoDetectSubtargetFeatures() {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
union {
unsigned u[3];
char c[12];
} text;
if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
return;
GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
if ((EDX >> 15) & 1) HasCMov = true;
if ((EDX >> 23) & 1) X86SSELevel = MMX;
if ((EDX >> 25) & 1) X86SSELevel = SSE1;
if ((EDX >> 26) & 1) X86SSELevel = SSE2;
if (ECX & 0x1) X86SSELevel = SSE3;
if ((ECX >> 9) & 1) X86SSELevel = SSSE3;
if ((ECX >> 19) & 1) X86SSELevel = SSE41;
if ((ECX >> 20) & 1) X86SSELevel = SSE42;
bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
HasCLMUL = IsIntel && ((ECX >> 1) & 0x1);
HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
HasAVX = ((ECX >> 28) & 0x1);
HasAES = IsIntel && ((ECX >> 25) & 0x1);
if (IsIntel || IsAMD) {
unsigned Family = 0;
unsigned Model = 0;
DetectFamilyModel(EAX, Family, Model);
IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
if (Family == 15 && Model == 26)
IsUAMemFast = true;
GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
HasX86_64 = (EDX >> 29) & 0x1;
HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
}
}
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
bool is64Bit)
: PICStyle(PICStyles::None)
, X86SSELevel(NoMMXSSE)
, X863DNowLevel(NoThreeDNow)
, HasCMov(false)
, HasX86_64(false)
, HasSSE4A(false)
, HasAVX(false)
, HasAES(false)
, HasCLMUL(false)
, HasFMA3(false)
, HasFMA4(false)
, IsBTMemSlow(false)
, IsUAMemFast(false)
, HasVectorUAMem(false)
, stackAlignment(8)
, MaxInlineSizeThreshold(128)
, TargetTriple(TT)
, Is64Bit(is64Bit) {
if (FloatABIType == FloatABI::Default)
FloatABIType = FloatABI::Hard;
if (!FS.empty()) {
std::string CPU = sys::getHostCPUName();
ParseSubtargetFeatures(FS, CPU);
} else {
AutoDetectSubtargetFeatures();
if (Is64Bit && X86SSELevel < SSE2)
X86SSELevel = SSE2;
}
if (Is64Bit) {
HasX86_64 = true;
HasCMov = true;
}
DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
<< ", 3DNowLevel " << X863DNowLevel
<< ", 64bit " << HasX86_64 << "\n");
assert((!Is64Bit || HasX86_64) &&
"64-bit code requested on a subtarget that doesn't support it!");
if (isTargetDarwin() || Is64Bit)
stackAlignment = 16;
if (StackAlignment)
stackAlignment = StackAlignment;
}
bool X86Subtarget::IsCalleePop(bool IsVarArg,
CallingConv::ID CallingConv) const {
if (IsVarArg)
return false;
switch (CallingConv) {
default:
return false;
case CallingConv::X86_StdCall:
return !is64Bit();
case CallingConv::X86_FastCall:
return !is64Bit();
case CallingConv::X86_ThisCall:
return !is64Bit();
case CallingConv::Fast:
return GuaranteedTailCallOpt;
case CallingConv::GHC:
return GuaranteedTailCallOpt;
}
}