#ifndef ARMBASEINFO_H
#define ARMBASEINFO_H
#include "llvm/Support/ErrorHandling.h"
#include "ARMGenRegisterNames.inc"
#include "ARMGenInstrNames.inc"
namespace llvm {
namespace ARMCC {
enum CondCodes { EQ, NE, HS, LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL };
inline static CondCodes getOppositeCondition(CondCodes CC) {
switch (CC) {
default: llvm_unreachable("Unknown condition code");
case EQ: return NE;
case NE: return EQ;
case HS: return LO;
case LO: return HS;
case MI: return PL;
case PL: return MI;
case VS: return VC;
case VC: return VS;
case HI: return LS;
case LS: return HI;
case GE: return LT;
case LT: return GE;
case GT: return LE;
case LE: return GT;
}
}
}
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
default: llvm_unreachable("Unknown condition code");
case ARMCC::EQ: return "eq";
case ARMCC::NE: return "ne";
case ARMCC::HS: return "hs";
case ARMCC::LO: return "lo";
case ARMCC::MI: return "mi";
case ARMCC::PL: return "pl";
case ARMCC::VS: return "vs";
case ARMCC::VC: return "vc";
case ARMCC::HI: return "hi";
case ARMCC::LS: return "ls";
case ARMCC::GE: return "ge";
case ARMCC::LT: return "lt";
case ARMCC::GT: return "gt";
case ARMCC::LE: return "le";
case ARMCC::AL: return "al";
}
}
namespace ARM_MB {
enum MemBOpt {
ST = 14,
ISH = 11,
ISHST = 10,
NSH = 7,
NSHST = 6,
OSH = 3,
OSHST = 2
};
inline static const char *MemBOptToString(unsigned val) {
switch (val) {
default: llvm_unreachable("Unknown memory operation");
case ST: return "st";
case ISH: return "ish";
case ISHST: return "ishst";
case NSH: return "nsh";
case NSHST: return "nshst";
case OSH: return "osh";
case OSHST: return "oshst";
}
}
}
inline static unsigned getARMRegisterNumbering(unsigned Reg) {
using namespace ARM;
switch (Reg) {
default:
llvm_unreachable("Unknown ARM register!");
case R0: case S0: case D0: case Q0: return 0;
case R1: case S1: case D1: case Q1: return 1;
case R2: case S2: case D2: case Q2: return 2;
case R3: case S3: case D3: case Q3: return 3;
case R4: case S4: case D4: case Q4: return 4;
case R5: case S5: case D5: case Q5: return 5;
case R6: case S6: case D6: case Q6: return 6;
case R7: case S7: case D7: case Q7: return 7;
case R8: case S8: case D8: case Q8: return 8;
case R9: case S9: case D9: case Q9: return 9;
case R10: case S10: case D10: case Q10: return 10;
case R11: case S11: case D11: case Q11: return 11;
case R12: case S12: case D12: case Q12: return 12;
case SP: case S13: case D13: case Q13: return 13;
case LR: case S14: case D14: case Q14: return 14;
case PC: case S15: case D15: case Q15: return 15;
case S16: case D16: return 16;
case S17: case D17: return 17;
case S18: case D18: return 18;
case S19: case D19: return 19;
case S20: case D20: return 20;
case S21: case D21: return 21;
case S22: case D22: return 22;
case S23: case D23: return 23;
case S24: case D24: return 24;
case S25: case D25: return 25;
case S26: case D26: return 26;
case S27: case D27: return 27;
case S28: case D28: return 28;
case S29: case D29: return 29;
case S30: case D30: return 30;
case S31: case D31: return 31;
}
}
namespace ARMII {
enum TOF {
MO_NO_FLAG,
MO_LO16,
MO_HI16,
MO_PLT
};
}
}
#endif