#include "apr_arch_atomic.h"
#ifdef USE_ATOMICS_PPC
#ifdef PPC405_ERRATA
# define PPC405_ERR77_SYNC " sync\n"
#else
# define PPC405_ERR77_SYNC
#endif
APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p)
{
return APR_SUCCESS;
}
APR_DECLARE(apr_uint32_t) apr_atomic_read32(volatile apr_uint32_t *mem)
{
return *mem;
}
APR_DECLARE(void) apr_atomic_set32(volatile apr_uint32_t *mem, apr_uint32_t val)
{
*mem = val;
}
APR_DECLARE(apr_uint32_t) apr_atomic_add32(volatile apr_uint32_t *mem, apr_uint32_t val)
{
apr_uint32_t prev, temp;
asm volatile ("loop_%=:\n"
" lwarx %0,0,%3\n"
" add %1,%0,%4\n"
PPC405_ERR77_SYNC
" stwcx. %1,0,%3\n"
" bne- loop_%=\n"
: "=&r" (prev), "=&r" (temp), "=m" (*mem)
: "b" (mem), "r" (val)
: "cc", "memory");
return prev;
}
APR_DECLARE(void) apr_atomic_sub32(volatile apr_uint32_t *mem, apr_uint32_t val)
{
apr_uint32_t temp;
asm volatile ("loop_%=:\n"
" lwarx %0,0,%2\n"
" subf %0,%3,%0\n"
PPC405_ERR77_SYNC
" stwcx. %0,0,%2\n"
" bne- loop_%=\n"
: "=&r" (temp), "=m" (*mem)
: "b" (mem), "r" (val)
: "cc", "memory");
}
APR_DECLARE(apr_uint32_t) apr_atomic_inc32(volatile apr_uint32_t *mem)
{
apr_uint32_t prev;
asm volatile ("loop_%=:\n"
" lwarx %0,0,%2\n"
" addi %0,%0,1\n"
PPC405_ERR77_SYNC
" stwcx. %0,0,%2\n"
" bne- loop_%=\n"
" subi %0,%0,1\n"
: "=&b" (prev), "=m" (*mem)
: "b" (mem), "m" (*mem)
: "cc", "memory");
return prev;
}
APR_DECLARE(int) apr_atomic_dec32(volatile apr_uint32_t *mem)
{
apr_uint32_t prev;
asm volatile ("loop_%=:\n"
" lwarx %0,0,%2\n"
" subi %0,%0,1\n"
PPC405_ERR77_SYNC
" stwcx. %0,0,%2\n"
" bne- loop_%=\n"
: "=&b" (prev), "=m" (*mem)
: "b" (mem), "m" (*mem)
: "cc", "memory");
return prev;
}
APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint32_t with,
apr_uint32_t cmp)
{
apr_uint32_t prev;
asm volatile ("loop_%=:\n"
" lwarx %0,0,%1\n"
" cmpw %0,%3\n"
" bne- exit_%=\n"
PPC405_ERR77_SYNC
" stwcx. %2,0,%1\n"
" bne- loop_%=\n"
"exit_%=:\n"
: "=&r" (prev)
: "b" (mem), "r" (with), "r" (cmp)
: "cc", "memory");
return prev;
}
APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(volatile apr_uint32_t *mem, apr_uint32_t val)
{
apr_uint32_t prev;
asm volatile ("loop_%=:\n"
" lwarx %0,0,%1\n"
PPC405_ERR77_SYNC
" stwcx. %2,0,%1\n"
" bne- loop_%="
: "=&r" (prev)
: "b" (mem), "r" (val)
: "cc", "memory");
return prev;
}
APR_DECLARE(void*) apr_atomic_casptr(volatile void **mem, void *with, const void *cmp)
{
void *prev;
#if APR_SIZEOF_VOIDP == 4
asm volatile ("loop_%=:\n"
" lwarx %0,0,%1\n"
" cmpw %0,%3\n"
" bne- exit_%=\n"
PPC405_ERR77_SYNC
" stwcx. %2,0,%1\n"
" bne- loop_%=\n"
"exit_%=:\n"
: "=&r" (prev)
: "b" (mem), "r" (with), "r" (cmp)
: "cc", "memory");
#elif APR_SIZEOF_VOIDP == 8
asm volatile ("loop_%=:\n"
" ldarx %0,0,%1\n"
" cmpd %0,%3\n"
" bne- exit_%=\n"
PPC405_ERR77_SYNC
" stdcx. %2,0,%1\n"
" bne- loop_%=\n"
"exit_%=:\n"
: "=&r" (prev)
: "b" (mem), "r" (with), "r" (cmp)
: "cc", "memory");
#else
#error APR_SIZEOF_VOIDP value not supported
#endif
return prev;
}
APR_DECLARE(void*) apr_atomic_xchgptr(volatile void **mem, void *with)
{
void *prev;
#if APR_SIZEOF_VOIDP == 4
asm volatile ("loop_%=:\n"
" lwarx %0,0,%1\n"
PPC405_ERR77_SYNC
" stwcx. %2,0,%1\n"
" bne- loop_%=\n"
" isync\n"
: "=&r" (prev)
: "b" (mem), "r" (with)
: "cc", "memory");
#elif APR_SIZEOF_VOIDP == 8
asm volatile ("loop_%=:\n"
" ldarx %0,0,%1\n"
PPC405_ERR77_SYNC
" stdcx. %2,0,%1\n"
" bne- loop_%=\n"
" isync\n"
: "=&r" (prev)
: "b" (mem), "r" (with)
: "cc", "memory");
#else
#error APR_SIZEOF_VOIDP value not supported
#endif
return prev;
}
#endif