#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86_ansic.h"
#include "xf86PciInfo.h"
#include "xf86Pci.h"
#include "tga_regs.h"
#include "tga.h"
#define IBM561_HEAD_MASK 0x01
#define IBM561_READ 0x02
#define IBM561_WRITE 0x00
#define RAMDAC_ONE_BYTE 0x0E000
#define RAMDAC_TWO_BYTES 0x0c000
#define RAMDAC_THREE_BYTES 0x08000
#define RAMDAC_FOUR_BYTES 0x00000
#define IBM561_ADDR_LOW 0x0000
#define IBM561_ADDR_HIGH 0x0100
#define IBM561_CMD_REGS 0x0200
#define IBM561_CMD_CURS_PIX 0x0200
#define IBM561_CMD_CURS_LUT 0x0300
#define IBM561_CMD_FB_WAT 0x0300
#define IBM561_CMD_AUXFB_WAT 0x0200
#define IBM561_CMD_OL_WAT 0x0300
#define IBM561_CMD_AUXOL_WAT 0x0200
#define IBM561_CMD_GAMMA 0x0300
#define IBM561_CMD_CMAP 0x0300
#define IBM561_ADDR_EPSR_SHIFT 0
#define IBM561_ADDR_EPDR_SHIFT 8
#define IBM561_CONFIG_REG_1 0x0001
#define IBM561_CONFIG_REG_2 0x0002
#define IBM561_CONFIG_REG_1 0x0001
#define IBM561_CONFIG_REG_2 0x0002
#define IBM561_CONFIG_REG_3 0x0003
#define IBM561_CONFIG_REG_4 0x0004
#define IBM561_WAT_SEG_REG 0x0006
#define IBM561_OL_SEG_REG 0x0007
#define IBM561_CHROMA_KEY_REG0 0x0010
#define IBM561_CHROMA_KEY_REG1 0x0011
#define IBM561_CHROMA_MASK_REG0 0x0012
#define IBM561_CHROMA_MASK_REG1 0x0013
#define IBM561_SYNC_CONTROL 0x0020
#define IBM561_PLL_VCO_DIV_REG 0x0021
#define IBM561_PLL_REF_REG 0x0022
#define IBM561_CURSOR_CTRL_REG 0x0030
#define IBM561_CURSOR_HS_REG 0x0034
#define IBM561_VRAM_MASK_REG 0x0050
#define IBM561_DAC_CTRL 0x005f
#define IBM561_DIV_DOT_CLK_REG 0x0082
#define IBM561_READ_MASK 0x0205
#define IBM561_BLINK_MASK 0x0209
#define IBM561_FB_WINDOW_TYPE_TABLE 0x1000
#define IBM561_AUXFB_WINDOW_TYPE_TABLE 0x0E00
#define IBM561_OL_WINDOW_TYPE_TABLE 0x1400
#define IBM561_AUXOL_WINDOW_TYPE_TABLE 0x0F00
#define IBM561_RED_GAMMA_TABLE 0x3000
#define IBM561_GREEN_GAMMA_TABLE 0x3400
#define IBM561_BLUE_GAMMA_TABLE 0x3800
#define IBM561_COLOR_LOOKUP_TABLE 0x4000
#define IBM561_CURSOR_LOOKUP_TABLE 0x0a11
#define IBM561_CURSOR_BLINK_TABLE 0x0a15
#define IBM561_CROSS_LOOKUP_TABLE 0x0a19
#define IBM561_CROSS_BLINK_TABLE 0x0a1d
#define IBM561_CURSOR_PIXMAP 0x2000
#define IBM561_CURSOR_X_LOW 0x0036
#define IBM561_CURSOR_X_HIGH 0x0037
#define IBM561_CURSOR_Y_LOW 0x0038
#define IBM561_CURSOR_Y_HIGH 0x0039
#define LO_ADDR (IBM561_ADDR_LOW | RAMDAC_ONE_BYTE)
#define HI_ADDR (IBM561_ADDR_HIGH | RAMDAC_ONE_BYTE)
#define REGS_ADDR (IBM561_CMD_REGS | RAMDAC_ONE_BYTE)
#define FBWAT_ADDR (IBM561_CMD_FB_WAT | RAMDAC_ONE_BYTE)
#define AUXFBWAT_ADDR (IBM561_CMD_AUXFB_WAT | RAMDAC_ONE_BYTE)
#define OLWAT_ADDR (IBM561_CMD_OL_WAT | RAMDAC_ONE_BYTE)
#define AUXOLWAT_ADDR (IBM561_CMD_AUXOL_WAT | RAMDAC_ONE_BYTE)
#define CMAP_ADDR (IBM561_CMD_CMAP | RAMDAC_ONE_BYTE)
#define GAMMA_ADDR (IBM561_CMD_GAMMA | RAMDAC_ONE_BYTE)
#define IBM561LoadAddr(reg) \
do { \
TGA2_WRITE_RAMDAC_REG((reg), LO_ADDR); \
TGA2_WRITE_RAMDAC_REG((reg) >> 8, HI_ADDR); \
} while (0)
unsigned char
IBM561ReadReg(ScrnInfoPtr pScrn, CARD32 reg)
{
TGAPtr pTga;
unsigned char ret;
pTga = TGAPTR(pScrn);
TGA2_WRITE_RAMDAC_REG(reg, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(reg >> 8, HI_ADDR);
ret = TGA2_READ_RAMDAC_REG(REGS_ADDR);
#if 1
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "IBM561ReadReg: reg 0x%lx data 0x%x\n",
(unsigned long)reg, ret);
#endif
return (ret);
}
void
IBM561WriteReg(ScrnInfoPtr pScrn, CARD32 reg,
#if 0
unsigned char mask, unsigned char data)
#else
unsigned char data)
#endif
{
TGAPtr pTga;
unsigned char tmp = 0x00;
pTga = TGAPTR(pScrn);
#if 0
if (mask != 0x00) {
TGA2_WRITE_RAMDAC_REG(reg, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(reg >> 8, HI_ADDR);
tmp = TGA2_READ_RAMDAC_REG(REGS_ADDR) & mask;
}
#endif
#if 1
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "IBM561WriteReg: reg 0x%lx data 0x%x\n",
(unsigned long)reg, tmp | data);
#endif
TGA2_WRITE_RAMDAC_REG(reg, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(reg >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG ((tmp | data), REGS_ADDR);
}
void
IBM561ramdacSave(ScrnInfoPtr pScrn, unsigned char *Ibm561)
{
#if 0
TGAPtr pTga = TGAPTR(pScrn);
int i, j;
Ibm561[0] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_CMD_REG_0);
Ibm561[1] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_CMD_REG_1);
Ibm561[2] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_CMD_REG_2);
Ibm561[3] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_0);
Ibm561[4] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_1);
Ibm561[5] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_2);
Ibm561[6] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_3);
Ibm561[7] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_0);
Ibm561[8] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_1);
Ibm561[9] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_2);
Ibm561[10] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_3);
IBM561_LOAD_ADDR(IBM561_WINDOW_TYPE_BASE);
TGA_WRITE_REG((IBM561_REG_ACC<<2)|0x2, TGA_RAMDAC_SETUP_REG);
for (i = 0, j = 11; i < 16; i++) {
Ibm561[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff;
Ibm561[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff;
Ibm561[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff;
}
#endif
}
static void
IBM561WindowTagsInit(ScrnInfoPtr pScrn)
{
TGAPtr pTga = TGAPTR(pScrn);
unsigned char low, high;
int i;
typedef struct {
unsigned char low_byte;
unsigned char high_byte;
}fb_wid_cell_t;
typedef struct {
unsigned char aux_fbwat;
} aux_fb_wid_cell_t;
typedef struct {
unsigned char low_byte;
unsigned char high_byte;
} ol_wid_cell_t;
typedef struct {
unsigned char aux_olwat;
} aux_ol_wid_cell_t;
#define TGA_RAMDAC_561_FB_WINDOW_TAG_COUNT 256
#define TGA_RAMDAC_561_FB_WINDOW_TAG_MAX_COUNT 16
#define TGA_RAMDAC_561_AUXFB_WINDOW_TAG_COUNT 16
#define TGA_RAMDAC_561_OL_WINDOW_TAG_COUNT 256
#define TGA_RAMDAC_561_OL_WINDOW_TAG_MAX_COUNT 16
#define TGA_RAMDAC_561_AUXOL_WINDOW_TAG_COUNT 16
#define TGA_RAMDAC_561_CMAP_ENTRY_COUNT 1024
#define TGA_RAMDAC_561_GAM_ENTRY_COUNT 256
static fb_wid_cell_t
fb_wids_561[TGA_RAMDAC_561_FB_WINDOW_TAG_COUNT] = {
#if 0
{0x28, 0x00},
#else
{0x36, 0x00},
#endif
{0x08, 0x00},
{0x00, 0x00},
{0x34, 0x00},
{0x28, 0x01},
{0x08, 0x01},
{0x00, 0x01},
{0x34, 0x01},
{0x1e, 0x00},
{0x14, 0x00},
{0x1e, 0x01},
{0x16, 0x01},
{0x36, 0x00},
{0x36, 0x00},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0}
};
static aux_fb_wid_cell_t
auxfb_wids_561[TGA_RAMDAC_561_AUXFB_WINDOW_TAG_COUNT] = {
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
{0x04},
};
static ol_wid_cell_t
ol_wids_561[TGA_RAMDAC_561_OL_WINDOW_TAG_COUNT] = {
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0x31, 0x02},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},
{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}
};
static aux_ol_wid_cell_t
auxol_wids_561[TGA_RAMDAC_561_AUXOL_WINDOW_TAG_COUNT] = {
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
{0x0c},
};
IBM561LoadAddr(IBM561_FB_WINDOW_TYPE_TABLE);
for ( i = 0; i < TGA_RAMDAC_561_FB_WINDOW_TAG_COUNT; i++ ) {
low = ((fb_wids_561[i].low_byte & 0xfc) >> 2);
high =((fb_wids_561[i].high_byte & 0x03) << 6) & 0xff;
TGA2_WRITE_RAMDAC_REG (low | high, FBWAT_ADDR);
low = (fb_wids_561[i].low_byte & 0x03) << 6;
TGA2_WRITE_RAMDAC_REG (low, FBWAT_ADDR);
}
IBM561LoadAddr(IBM561_AUXFB_WINDOW_TYPE_TABLE);
for ( i = 0; i < TGA_RAMDAC_561_AUXFB_WINDOW_TAG_COUNT; i++ ) {
TGA2_WRITE_RAMDAC_REG (auxfb_wids_561[i].aux_fbwat, AUXFBWAT_ADDR);
}
IBM561LoadAddr(IBM561_OL_WINDOW_TYPE_TABLE);
for ( i = 0; i < TGA_RAMDAC_561_OL_WINDOW_TAG_COUNT; i++ ) {
low = ((ol_wids_561[i].low_byte & 0xfc) >> 2);
high =((ol_wids_561[i].high_byte & 0x03) << 6) & 0xff;
TGA2_WRITE_RAMDAC_REG (low | high, OLWAT_ADDR);
low = (ol_wids_561[i].low_byte & 0x03) << 6;
TGA2_WRITE_RAMDAC_REG (low, OLWAT_ADDR);
}
IBM561LoadAddr(IBM561_AUXOL_WINDOW_TYPE_TABLE);
for ( i = 0; i < TGA_RAMDAC_561_AUXOL_WINDOW_TAG_COUNT; i++ ) {
TGA2_WRITE_RAMDAC_REG (auxol_wids_561[i].aux_olwat, AUXOLWAT_ADDR);
}
}
static int
IBM561InitColormap(ScrnInfoPtr pScrn)
{
TGAPtr pTga = TGAPTR(pScrn);
#if 0
tga_ibm561_info_t *bti = (tga_ibm561_info_t *) closure;
tga_info_t *tgap = tga_softc[bti->unit];
#endif
int i;
TGA2_WRITE_RAMDAC_REG(IBM561_COLOR_LOOKUP_TABLE, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_COLOR_LOOKUP_TABLE >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
for ( i = 1; i <256; i++ ) {
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
}
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
for ( i = 1; i <256; i++ ) {
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
}
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
for ( i = 1; i <256; i++ ) {
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
}
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR);
for ( i = 1; i <256; i++ ) {
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR);
}
TGA2_WRITE_RAMDAC_REG(IBM561_RED_GAMMA_TABLE, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_RED_GAMMA_TABLE >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR);
for ( i = 1; i <256; i++ ) {
TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR);
}
TGA2_WRITE_RAMDAC_REG(IBM561_GREEN_GAMMA_TABLE, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_GREEN_GAMMA_TABLE >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR);
for ( i = 1; i <256; i++ ) {
TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR);
}
TGA2_WRITE_RAMDAC_REG(IBM561_BLUE_GAMMA_TABLE, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_BLUE_GAMMA_TABLE >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR);
for ( i = 1; i <256; i++ ) {
TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR);
}
#if 0
bti->cursor_fg.red = bti->cursor_fg.green = bti->cursor_fg.blue
= 0xffff;
bti->cursor_bg.red = bti->cursor_bg.green = bti->cursor_bg.blue
= 0x0000;
tga_ibm561_restore_cursor_color( closure, 0 );
#endif
return 0;
}
void
IBM561ramdacHWInit(ScrnInfoPtr pScrn)
{
TGAPtr pTga = TGAPTR(pScrn);
unsigned int temp1[6] = {0,0,0,0,0,0};
temp1[0] = 0x00000101;
temp1[1] = 0x01000000;
temp1[2] = 0x00000001;
temp1[3] = 0x00010000;
temp1[4] = 0x01010100;
temp1[5] = 0x01000000;
write_av9110(pScrn, temp1);
IBM561WriteReg(pScrn, IBM561_CONFIG_REG_1, 0x2a );
IBM561WriteReg(pScrn, IBM561_CONFIG_REG_3, 0x41 );
IBM561WriteReg(pScrn, IBM561_CONFIG_REG_4, 0x20 );
IBM561WriteReg(pScrn, IBM561_PLL_VCO_DIV_REG, tga_c_table->ibm561_vco_div);
IBM561WriteReg(pScrn, IBM561_PLL_REF_REG, tga_c_table->ibm561_ref );
IBM561WriteReg(pScrn, IBM561_DIV_DOT_CLK_REG, 0xb0 );
IBM561WriteReg(pScrn, IBM561_SYNC_CONTROL, 0x01 );
IBM561WriteReg(pScrn, IBM561_CONFIG_REG_2, 0x19 );
TGA_WRITE_REG(0xFFFFFFFF, TGA_PLANEMASK_REG);
IBM561WriteReg(pScrn, IBM561_CONFIG_REG_1, 0x2a );
IBM561WriteReg(pScrn, IBM561_CONFIG_REG_4, 0x20 );
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_WAT_SEG_REG, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_WAT_SEG_REG >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_CHROMA_KEY_REG0, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_CHROMA_KEY_REG0 >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
IBM561WriteReg(pScrn, IBM561_CURSOR_CTRL_REG, 0);
TGA2_WRITE_RAMDAC_REG(IBM561_CURSOR_HS_REG, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_CURSOR_HS_REG >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_VRAM_MASK_REG, LO_ADDR);
TGA2_WRITE_RAMDAC_REG(IBM561_VRAM_MASK_REG >> 8, HI_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR);
IBM561InitColormap(pScrn);
IBM561WindowTagsInit(pScrn);
}
void
IBM561ramdacRestore(ScrnInfoPtr pScrn, unsigned char *Ibm561)
{
#if 0
TGAPtr pTga = TGAPTR(pScrn);
#endif
#if 0
int i, j;
IBM561_WRITE(IBM561_REG_ACC, IBM561_CMD_REG_0, Ibm561[0]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_CMD_REG_1, Ibm561[1]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_CMD_REG_2, Ibm561[2]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_0, Ibm561[3]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_1, Ibm561[4]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_2, Ibm561[5]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_3, Ibm561[6]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_0, Ibm561[7]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_1, Ibm561[8]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_2, Ibm561[9]);
IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_3, Ibm561[10]);
IBM561_LOAD_ADDR(IBM561_WINDOW_TYPE_BASE);
TGA_WRITE_REG((IBM561_REG_ACC<<2), TGA_RAMDAC_SETUP_REG);
for (i = 0, j = 11; i < 16; i++) {
TGA_WRITE_REG(Ibm561[j++]|(IBM561_REG_ACC<<10), TGA_RAMDAC_REG);
TGA_WRITE_REG(Ibm561[j++]|(IBM561_REG_ACC<<10), TGA_RAMDAC_REG);
TGA_WRITE_REG(Ibm561[j++]|(IBM561_REG_ACC<<10), TGA_RAMDAC_REG);
}
#endif
}