#ifndef __COMMONREGS_H__
#define __COMMONREGS_H__
#define FIFO_SIZE 0x1f
#define FIFO_SWAP_NO 0x00
#define FIFO_SWAP_END 0x04
#define FIFO_SWAP_INHW 0x08
#define FIFO_SWAP_HW 0x0c
#define FIFOINFREE 0x40
#define FIFOOUTVALID 0x41
#define COMM 0x42
#define MEMENDIAN 0x43
#define INTR 0x44
#define INTREN 0x46
#define DEBUGREG 0x48
#define LOWWATERMARK 0x49
#define PCITEST 0x4C
#define DMACMDPTR 0x50
#define DMA_ADDRESS 0x54
#define DMA_COUNT 0x58
#define STATEINDEX 0x60
#define STATEDATA 0x64
#define SCRATCH 0x70
#define MODEREG 0x72
#define MODE_ MODEREG
#define MODE MODEREG
#define BANKSELECT 0x74
#define BANKSELECT_PHYSADDR ((unsigned long)(0xA0000))
#define CRTCTEST 0x80
#define CRTCCTL 0x84
#define CRTCHORZ 0x88
#define CRTCVERT 0x8c
#define FRAMEBASEB 0x90
#define FRAMEBASEA 0x94
#define CRTCOFFSET 0x98
#define CRTCSTATUS 0x9c
#define DRAMCTL 0xa0
#define PALETTE 0xb0
#define RAMDACBASEADDR 0xb0
#define DEVICE0 0xc0
#define DEVICE1 0xd0
#define SYSSTATUS_MASK 0x0f
#define SYSSTATUS_SHIFT 0
#define RISCSTATUS_MASK 0xf0
#define RISCSTATUS_SHIFT 4
#define MEMENDIAN_NO 0
#define MEMENDIAN_END 1
#define MEMENDIAN_INHW 2
#define MEMENDIAN_HW 3
#define MEMENDIAN_MASK 3
#define MEMENDIAN_SHIFT 0
#define DMABUSY 0x80
#define DMACMDPTR_DMABUSY 0x1
#define VERTINTR 0x01
#define FIFOLOWINTR 0x02
#define RISCINTR 0x04
#define HALTINTR 0x08
#define FIFOERRORINTR 0x10
#define DMAERRORINTR 0x20
#define DMAINTR 0x40
#define XINTR 0x80
#define VERTINTREN 0x01
#define FIFOLOWINTREN 0x02
#define RISCINTREN 0x04
#define HALTINTREN 0x08
#define FIFOERRORINTREN 0x10
#define DMAERRORINTREN 0x20
#define DMAINTREN 0x40
#define XINTREN 0x80
#define SOFTRESET 0x01
#define HOLDRISC 0x02
#define STEPRISC 0x04
#define DIRECTSCLK 0x08
#define SOFTVGARESET 0x10
#define SOFTXRESET 0x20
#define VESA_MODE 0x01
#define VGA_MODE 0x02
#define VGA_32 0x04
#define DMA_EN 0x08
#define NATIVE_MODE 0
#define DRAMCTL_ADDR 0xffe00500
#define DRAMCTL_SLOWPRECHARGE 0x140010
#define DRAMCTL_NORMAL 0x140000
#define CRTCTEST_ADDR 0xffe00400
#define CRTCCTL_ADDR 0xffe00420
#define CRTCHORZ_ADDR 0xffe00440
#define CRTCVERT_ADDR 0xffe00460
#define FRAMEBASEB_ADDR 0xffe00480
#define FRAMEBASEA_ADDR 0xffe004a0
#define CRTCOFFSET_ADDR 0xffe004c0
#define CRTCSTATUS_ADDR 0xffe004e0
#define CRTCTEST_VIDEOLATENCY_MASK 0x1F
#define CRTCTEST_NOTVBLANK 0x10000
#define CRTCTEST_VBLANK 0x40000
#define CRTCCTL_SCRNFMT_MASK 0xF
#define CRTCCTL_VIDEOFIFOSIZE128 0x10
#define CRTCCTL_ENABLEDDC 0x20
#define CRTCCTL_DDCOUTPUT 0x40
#define CRTCCTL_DDCDATA 0x80
#define CRTCCTL_VSYNCHI 0x100
#define CRTCCTL_HSYNCHI 0x200
#define CRTCCTL_VSYNCENABLE 0x400
#define CRTCCTL_HSYNCENABLE 0x800
#define CRTCCTL_VIDEOENABLE 0x1000
#define CRTCCTL_STEREOSCOPIC 0x2000
#define CRTCCTL_FRAMEDISPLAYED 0x4000
#define CRTCCTL_FRAMEBUFFERBGR 0x8000
#define CRTCCTL_EVENFRAME 0x10000
#define CRTCCTL_LINEDOUBLE 0x20000
#define CRTCCTL_FRAMESWITCHED 0x40000
#define CRTCHORZ_ACTIVE_MASK 0xFF
#define CRTCHORZ_ACTIVE_SHIFT 0
#define CRTCHORZ_BACKPORCH_MASK 0x7E00
#define CRTCHORZ_BACKPORCH_SHIFT 11
#define CRTCHORZ_SYNC_MASK 0x1F0000L
#define CRTCHORZ_SYNC_SHIFT 16
#define CRTCHORZ_FRONTPORCH_MASK 0xE00000L
#define CRTCHORZ_FRONTPORCH_SHIFT 20
#define CRTCVERT_ACTIVE_MASK 0x7FF
#define CRTCVERT_BACKPORCH_MASK 0x1F800
#define CRTCVERT_SYNC_MASK 0xE0000
#define CRTCVERT_FRONTPORCH_MASK 0x03F00000
#define CRTCOFFSET_MASK 0xFFFF
#define CRTCSTATUS_HORZCLOCKS_MASK 0xFF
#define CRTCSTATUS_HORZ_MASK 0x600
#define CRTCSTATUS_HORZ_FPORCH 0x200
#define CRTCSTATUS_HORZ_SYNC 0x600
#define CRTCSTATUS_HORZ_BPORCH 0x400
#define CRTCSTATUS_HORZ_ACTIVE 0x000
#define CRTCSTATUS_SCANLINESLEFT_MASK 0x003FF800
#define CRTCSTATUS_VERT_MASK 0xC00000
#define CRTCSTATUS_VERT_FPORCH 0x400000
#define CRTCSTATUS_VERT_SYNC 0xC00000
#define CRTCSTATUS_VERT_BPORCH 0x800000
#define CRTCSTATUS_VERT_ACTIVE 0x000000
#define DACRAMWRITEADR 0xb0
#define DACRAMDATA 0xb1
#define DACPIXELMSK 0xb2
#define DACRAMREADADR 0xb3
#define DACOVSWRITEADR 0xb4
#define DACOVSDATA 0xb5
#define DACCOMMAND0 0xb6
#define DACOVSREADADR 0xb7
#define DACCOMMAND1 0xb8
#define DACCOMMAND2 0xb9
#define DACSTATUS 0xba
#define DACCOMMAND3 0xba
#define DACCURSORDATA 0xbb
#define DACCURSORXLOW 0xbc
#define DACCURSORXHIGH 0xbd
#define DACCURSORYLOW 0xbe
#define DACCURSORYHIGH 0xbf
#define DACCOMMAND3_INIT 0x00
#define DAC_CLK_DOUBLER 0x8
#define PLLDEV DEVICE0
#define STATEINDEX_IR 128
#define STATEINDEX_PC 129
#define STATEINDEX_S1 130
#define CONFIGIOREG 0xE0000014
#define CONFIGENABLE 0xE0000004
#ifdef USEROM
#define CONFIGROMREG 0xE0000030
#endif
#define ICACHESIZE 2048
#define ICACHELINESIZE 32
#define ICACHE_ONOFF_MASK (((vu32)1<<17)|(1<<3))
#define ICACHE_ON ((0<<17)|(0<<3))
#define ICACHE_OFF (((vu32)1<<17)|(1<<3))
#endif