#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86_ansic.h"
#include "compiler.h"
#include "xf86PciInfo.h"
#include "xf86Pci.h"
#include "xf86Version.h"
#include "ct_driver.h"
#define CHIPS_MONO_STAT_1 0x3BA
#define CHIPS_STAT_0 0x3BA
#define CHIPS_MSS 0x3CB
#define CHIPS_IOSS 0x3CD
#define CHIPS_FR_INDEX 0x3D0
#define CHIPS_FR_DATA 0x3D1
#define CHIPS_MR_INDEX 0x3D2
#define CHIPS_MR_DATA 0x3D3
#define CHIPS_XR_INDEX 0x3D6
#define CHIPS_XR_DATA 0x3D7
#define CHIPS_COLOR_STAT_1 0x3DA
#define CHIPS_MMIO_MONO_CRTC_INDEX 0x768
#define CHIPS_MMIO_MONO_CRTC_DATA 0x769
#define CHIPS_MMIO_MONO_STAT_1 0x774
#define CHIPS_MMIO_ATTR_INDEX 0x780
#define CHIPS_MMIO_ATTR_DATA_W 0x780
#define CHIPS_MMIO_ATTR_DATA_R 0x781
#define CHIPS_MMIO_STAT_0 0x784
#define CHIPS_MMIO_MISC_OUT_W 0x784
#define CHIPS_MMIO_SEQ_INDEX 0x788
#define CHIPS_MMIO_SEQ_DATA 0x789
#define CHIPS_MMIO_DAC_MASK 0x78C
#define CHIPS_MMIO_DAC_READ_ADDR 0x78D
#define CHIPS_MMIO_DAC_WRITE_ADDR 0x790
#define CHIPS_MMIO_DAC_DATA 0x791
#define CHIPS_MMIO_FEATURE_R 0x794
#define CHIPS_MMIO_MSS 0x795
#define CHIPS_MMIO_MISC_OUT_R 0x798
#define CHIPS_MMIO_IOSS 0x799
#define CHIPS_MMIO_GRAPH_INDEX 0x79C
#define CHIPS_MMIO_GRAPH_DATA 0x79D
#define CHIPS_MMIO_FR_INDEX 0x7A0
#define CHIPS_MMIO_FR_DATA 0x7A1
#define CHIPS_MMIO_MR_INDEX 0x7A4
#define CHIPS_MMIO_MR_DATA 0x7A5
#define CHIPS_MMIO_COLOR_CRTC_INDEX 0x7A8
#define CHIPS_MMIO_COLOR_CRTC_DATA 0x7A9
#define CHIPS_MMIO_XR_INDEX 0x7AC
#define CHIPS_MMIO_XR_DATA 0x7AD
#define CHIPS_MMIO_COLOR_STAT_1 0x7B4
void
chipsStdWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
outb(cPtr->PIOBase + CHIPS_XR_DATA, value);
}
static CARD8
chipsStdReadXR(CHIPSPtr cPtr, CARD8 index)
{
outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
return inb(cPtr->PIOBase + CHIPS_XR_DATA);
}
static void
chipsStdWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
outb(cPtr->PIOBase + CHIPS_FR_DATA, value);
}
static CARD8
chipsStdReadFR(CHIPSPtr cPtr, CARD8 index)
{
outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
return inb(cPtr->PIOBase + CHIPS_FR_DATA);
}
static void
chipsStdWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
outb(cPtr->PIOBase + CHIPS_MR_DATA, value);
}
static CARD8
chipsStdReadMR(CHIPSPtr cPtr, CARD8 index)
{
outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
return inb(cPtr->PIOBase + CHIPS_MR_DATA);
}
static void
chipsStdWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_MSS, value);
}
static CARD8
chipsStdReadMSS(CHIPSPtr cPtr)
{
return inb(cPtr->PIOBase + CHIPS_MSS);
}
static void
chipsStdWriteIOSS(CHIPSPtr cPtr, CARD8 value)
{
outb(cPtr->PIOBase + CHIPS_IOSS, value);
}
static CARD8
chipsStdReadIOSS(CHIPSPtr cPtr)
{
return inb(cPtr->PIOBase + CHIPS_IOSS);
}
void
CHIPSSetStdExtFuncs(CHIPSPtr cPtr)
{
cPtr->writeFR = chipsStdWriteFR;
cPtr->readFR = chipsStdReadFR;
cPtr->writeMR = chipsStdWriteMR;
cPtr->readMR = chipsStdReadMR;
cPtr->writeXR = chipsStdWriteXR;
cPtr->readXR = chipsStdReadXR;
cPtr->writeMSS = chipsStdWriteMSS;
cPtr->readMSS = chipsStdReadMSS;
cPtr->writeIOSS = chipsStdWriteIOSS;
cPtr->readIOSS = chipsStdReadIOSS;
}
#define chipsminb(p) MMIO_IN8(cPtr->MMIOBaseVGA, (p))
#define chipsmoutb(p,v) MMIO_OUT8(cPtr->MMIOBaseVGA, (p),(v))
static void
chipsMmioWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
chipsmoutb(CHIPS_MMIO_XR_DATA, value);
}
static CARD8
chipsMmioReadXR(CHIPSPtr cPtr, CARD8 index)
{
chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
return chipsminb(CHIPS_MMIO_XR_DATA);
}
static void
chipsMmioWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
chipsmoutb(CHIPS_MMIO_FR_DATA, value);
}
static CARD8
chipsMmioReadFR(CHIPSPtr cPtr, CARD8 index)
{
chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
return chipsminb(CHIPS_MMIO_FR_DATA);
}
static void
chipsMmioWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
chipsmoutb(CHIPS_MMIO_MR_DATA, value);
}
static CARD8
chipsMmioReadMR(CHIPSPtr cPtr, CARD8 index)
{
chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
return chipsminb(CHIPS_MMIO_MR_DATA);
}
static void
chipsMmioWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
{
if ((value & MSS_SHADOW) == MSS_PIPE_B)
cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeB;
else
cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeA;
hwp->MMIOBase = cPtr->MMIOBaseVGA;
chipsmoutb(CHIPS_MMIO_MSS, value);
}
static CARD8
chipsMmioReadMSS(CHIPSPtr cPtr)
{
return chipsminb(CHIPS_MMIO_MSS);
}
static void
chipsMmioWriteIOSS(CHIPSPtr cPtr, CARD8 value)
{
chipsmoutb(CHIPS_MMIO_IOSS, value);
}
static CARD8
chipsMmioReadIOSS(CHIPSPtr cPtr)
{
return chipsminb(CHIPS_MMIO_IOSS);
}
void
CHIPSSetMmioExtFuncs(CHIPSPtr cPtr)
{
cPtr->writeFR = chipsMmioWriteFR;
cPtr->readFR = chipsMmioReadFR;
cPtr->writeMR = chipsMmioWriteMR;
cPtr->readMR = chipsMmioReadMR;
cPtr->writeXR = chipsMmioWriteXR;
cPtr->readXR = chipsMmioReadXR;
cPtr->writeMSS = chipsMmioWriteMSS;
cPtr->readMSS = chipsMmioReadMSS;
cPtr->writeIOSS = chipsMmioWriteIOSS;
cPtr->readIOSS = chipsMmioReadIOSS;
}
#define minb(p) MMIO_IN8(hwp->MMIOBase, (p))
#define moutb(p,v) MMIO_OUT8(hwp->MMIOBase, (p),(v))
static void
chipsMmioWriteCrtc(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
if (hwp->IOBase == VGA_IOBASE_MONO) {
moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
moutb(CHIPS_MMIO_MONO_CRTC_DATA, value);
} else {
moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
moutb(CHIPS_MMIO_COLOR_CRTC_DATA, value);
}
}
static CARD8
chipsMmioReadCrtc(vgaHWPtr hwp, CARD8 index)
{
if (hwp->IOBase == VGA_IOBASE_MONO) {
moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
return minb(CHIPS_MMIO_MONO_CRTC_DATA);
} else {
moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
return minb(CHIPS_MMIO_COLOR_CRTC_DATA);
}
}
static void
chipsMmioWriteGr(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
moutb(CHIPS_MMIO_GRAPH_INDEX, index);
moutb(CHIPS_MMIO_GRAPH_DATA, value);
}
static CARD8
chipsMmioReadGr(vgaHWPtr hwp, CARD8 index)
{
moutb(CHIPS_MMIO_GRAPH_INDEX, index);
return minb(CHIPS_MMIO_GRAPH_DATA);
}
static void
chipsMmioWriteSeq(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
moutb(CHIPS_MMIO_SEQ_INDEX, index);
moutb(CHIPS_MMIO_SEQ_DATA, value);
}
static CARD8
chipsMmioReadSeq(vgaHWPtr hwp, CARD8 index)
{
moutb(CHIPS_MMIO_SEQ_INDEX, index);
return minb(CHIPS_MMIO_SEQ_DATA);
}
static void
chipsMmioWriteAttr(vgaHWPtr hwp, CARD8 index, CARD8 value)
{
if (hwp->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, index);
moutb(CHIPS_MMIO_ATTR_DATA_W, value);
}
static CARD8
chipsMmioReadAttr(vgaHWPtr hwp, CARD8 index)
{
if (hwp->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, index);
return minb(CHIPS_MMIO_ATTR_DATA_R);
}
static void
chipsMmioWriteMiscOut(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_MISC_OUT_W, value);
}
static CARD8
chipsMmioReadMiscOut(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_MISC_OUT_R);
}
static void
chipsMmioEnablePalette(vgaHWPtr hwp)
{
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, 0x00);
hwp->paletteEnabled = TRUE;
}
static void
chipsMmioDisablePalette(vgaHWPtr hwp)
{
if (hwp->IOBase == VGA_IOBASE_MONO)
(void) minb(CHIPS_MMIO_MONO_STAT_1);
else
(void) minb(CHIPS_MMIO_COLOR_STAT_1);
moutb(CHIPS_MMIO_ATTR_INDEX, 0x20);
hwp->paletteEnabled = FALSE;
}
static void
chipsMmioWriteDacMask(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_MASK, value);
}
static CARD8
chipsMmioReadDacMask(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_DAC_MASK);
}
static void
chipsMmioWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_READ_ADDR, value);
}
static void
chipsMmioWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_WRITE_ADDR, value);
}
static void
chipsMmioWriteDacData(vgaHWPtr hwp, CARD8 value)
{
moutb(CHIPS_MMIO_DAC_DATA, value);
}
static CARD8
chipsMmioReadDacData(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_DAC_DATA);
}
static CARD8
chipsMmioReadST00(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_STAT_0);
}
static CARD8
chipsMmioReadST01(vgaHWPtr hwp)
{
if (hwp->IOBase == VGA_IOBASE_MONO)
return minb(CHIPS_MMIO_MONO_STAT_1);
else
return minb(CHIPS_MMIO_COLOR_STAT_1);
}
static CARD8
chipsMmioReadFCR(vgaHWPtr hwp)
{
return minb(CHIPS_MMIO_FEATURE_R);
}
static void
chipsMmioWriteFCR(vgaHWPtr hwp, CARD8 value)
{
if (hwp->IOBase == VGA_IOBASE_MONO) {
moutb(CHIPS_MMIO_MONO_STAT_1, value);
} else {
moutb(CHIPS_MMIO_COLOR_STAT_1, value);
}
}
void
CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
hwp->writeCrtc = chipsMmioWriteCrtc;
hwp->readCrtc = chipsMmioReadCrtc;
hwp->writeGr = chipsMmioWriteGr;
hwp->readGr = chipsMmioReadGr;
hwp->writeAttr = chipsMmioWriteAttr;
hwp->readAttr = chipsMmioReadAttr;
hwp->writeSeq = chipsMmioWriteSeq;
hwp->readSeq = chipsMmioReadSeq;
hwp->writeMiscOut = chipsMmioWriteMiscOut;
hwp->readMiscOut = chipsMmioReadMiscOut;
hwp->enablePalette = chipsMmioEnablePalette;
hwp->disablePalette = chipsMmioDisablePalette;
hwp->writeDacMask = chipsMmioWriteDacMask;
hwp->readDacMask = chipsMmioReadDacMask;
hwp->writeDacWriteAddr = chipsMmioWriteDacWriteAddr;
hwp->writeDacReadAddr = chipsMmioWriteDacReadAddr;
hwp->writeDacData = chipsMmioWriteDacData;
hwp->readDacData = chipsMmioReadDacData;
hwp->readST00 = chipsMmioReadST00;
hwp->readST01 = chipsMmioReadST01;
hwp->readFCR = chipsMmioReadFCR;
hwp->writeFCR = chipsMmioWriteFCR;
hwp->MMIOBase = base;
hwp->MMIOOffset = offset;
}