#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86_ansic.h"
#include "compiler.h"
#include "xf86PciInfo.h"
#include "xf86Pci.h"
#include "xf86Version.h"
#include "xf86Resources.h"
#include "vgaHW.h"
#include "mipointer.h"
#include "mibstore.h"
#include "mibank.h"
#include "micmap.h"
#include "fb.h"
#include "cfb8_16.h"
#include "xf1bpp.h"
#include "xf4bpp.h"
#include "xf86RAC.h"
#include "xf86int10.h"
#include "vbe.h"
#include "shadowfb.h"
#include "xf86cmap.h"
#include "dixstruct.h"
#include "ct_driver.h"
static const OptionInfoRec * CHIPSAvailableOptions(int chipid, int busid);
static void CHIPSIdentify(int flags);
static Bool CHIPSProbe(DriverPtr drv, int flags);
static Bool CHIPSPreInit(ScrnInfoPtr pScrn, int flags);
static Bool CHIPSScreenInit(int Index, ScreenPtr pScreen, int argc,
char **argv);
static Bool CHIPSEnterVT(int scrnIndex, int flags);
static void CHIPSLeaveVT(int scrnIndex, int flags);
static Bool CHIPSCloseScreen(int scrnIndex, ScreenPtr pScreen);
static void CHIPSFreeScreen(int scrnIndex, int flags);
static ModeStatus CHIPSValidMode(int scrnIndex, DisplayModePtr mode,
Bool verbose, int flags);
static Bool CHIPSSaveScreen(ScreenPtr pScreen, int mode);
static int chipsFindIsaDevice(GDevPtr dev);
static Bool chipsClockSelect(ScrnInfoPtr pScrn, int no);
Bool chipsModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
static void chipsSave(ScrnInfoPtr pScrn, vgaRegPtr VgaSave,
CHIPSRegPtr ChipsSave);
static void chipsRestore(ScrnInfoPtr pScrn, vgaRegPtr VgaReg,
CHIPSRegPtr ChipsReg, Bool restoreFonts);
static void chipsLock(ScrnInfoPtr pScrn);
static void chipsUnlock(ScrnInfoPtr pScrn);
static void chipsClockSave(ScrnInfoPtr pScrn, CHIPSClockPtr Clock);
static void chipsClockLoad(ScrnInfoPtr pScrn, CHIPSClockPtr Clock);
static Bool chipsClockFind(ScrnInfoPtr pScrn, int no, CHIPSClockPtr Clock);
static void chipsCalcClock(ScrnInfoPtr pScrn, int Clock,
unsigned char *vclk);
static int chipsGetHWClock(ScrnInfoPtr pScrn);
static Bool chipsPreInit655xx(ScrnInfoPtr pScrn, int flags);
static Bool chipsPreInitHiQV(ScrnInfoPtr pScrn, int flags);
static Bool chipsPreInitWingine(ScrnInfoPtr pScrn, int flags);
static int chipsSetMonitor(ScrnInfoPtr pScrn);
static Bool chipsMapMem(ScrnInfoPtr pScrn);
static Bool chipsUnmapMem(ScrnInfoPtr pScrn);
static void chipsProtect(ScrnInfoPtr pScrn, Bool on);
static void chipsBlankScreen(ScrnInfoPtr pScrn, Bool unblank);
static void chipsRestoreExtendedRegs(ScrnInfoPtr pScrn, CHIPSRegPtr Regs);
static void chipsRestoreStretching(ScrnInfoPtr pScrn,
unsigned char ctHorizontalStretch,
unsigned char ctVerticalStretch);
static Bool chipsModeInitHiQV(ScrnInfoPtr pScrn, DisplayModePtr mode);
static Bool chipsModeInitWingine(ScrnInfoPtr pScrn, DisplayModePtr mode);
static Bool chipsModeInit655xx(ScrnInfoPtr pScrn, DisplayModePtr mode);
static int chipsVideoMode(int vgaBitsPerPixel,int displayHSize,
int displayVSize);
static void chipsDisplayPowerManagementSet(ScrnInfoPtr pScrn,
int PowerManagementMode, int flags);
static void chipsHWCursorOn(CHIPSPtr cPtr, ScrnInfoPtr pScrn);
static void chipsHWCursorOff(CHIPSPtr cPtr, ScrnInfoPtr pScrn);
static void chipsFixResume(ScrnInfoPtr pScrn);
static void chipsLoadPalette(ScrnInfoPtr pScrn, int numColors,
int *indices, LOCO *colors, VisualPtr pVisual);
static void chipsLoadPalette16(ScrnInfoPtr pScrn, int numColors,
int *indices, LOCO *colors, VisualPtr pVisual);
static void chipsSetPanelType(CHIPSPtr cPtr);
static void chipsBlockHandler(int, pointer, pointer, pointer);
static int pix24bpp = 0;
static int CHIPSEntityIndex = -1;
#define SAR04
int ChipsAluConv[] =
{
0x00,
0x88,
0x44,
0xCC,
0x22,
0xAA,
0x66,
0xEE,
0x11,
0x99,
0x55,
0xDD,
0x33,
0xBB,
0x77,
0xFF,
};
int ChipsAluConv2[] =
{
0x00,
0xA0,
0x50,
0xF0,
0x0A,
0xAA,
0x5A,
0xFA,
0x05,
0xA5,
0x55,
0xF5,
0x0F,
0xAF,
0x5F,
0xFF,
};
int ChipsAluConv3[] =
{
0x0A,
0x8A,
0x4A,
0xCA,
0x2A,
0xAA,
0x6A,
0xEA,
0x1A,
0x9A,
0x5A,
0xDA,
0x3A,
0xBA,
0x7A,
0xFA,
};
unsigned int ChipsReg32HiQV[] =
{
0x00,
0x04,
0x08,
0x0C,
0x10,
0x14,
0x18,
0x1C,
0x20
};
unsigned int ChipsReg32[] =
{
0x83D0,
0x87D0,
0x8BD0,
0x8FD0,
0x93D0,
0x97D0,
0x9BD0,
0x9FD0,
0xA3D0,
0xA7D0,
0xABD0,
0xAFD0,
0xB3D0,
};
#if defined(__arm32__) && defined(__NetBSD__)
static DisplayModeRec ChipsPALMode = {
NULL, NULL,
"PAL",
MODE_OK,
M_T_BUILTIN,
15000,
776,
800,
872,
960,
0,
585,
590,
595,
625,
0,
V_INTERLACE,
-1,
15000,
776,
800,
800,
872,
872,
960,
0,
585,
590,
590,
595,
595,
625,
FALSE,
FALSE,
0,
NULL,
0.0,
0.0
};
static DisplayModeRec ChipsSECAMMode = {
NULL,
&ChipsPALMode,
"SECAM",
MODE_OK,
M_T_BUILTIN,
15000,
776,
800,
872,
960,
0,
585,
590,
595,
625,
0,
V_INTERLACE,
-1,
15000,
776,
800,
800,
872,
872,
960,
0,
585,
590,
590,
595,
595,
625,
FALSE,
FALSE,
0,
NULL,
0.0,
0.0
};
static DisplayModeRec ChipsNTSCMode = {
NULL,
&ChipsSECAMMode,
"NTSC",
MODE_OK,
M_T_BUILTIN,
11970,
584,
640,
696,
760,
0,
450,
479,
485,
525,
0,
V_INTERLACE | V_NVSYNC | V_NHSYNC ,
-1,
11970,
584,
640,
640,
696,
696,
760,
0,
450,
479,
479,
485,
485,
525,
FALSE,
FALSE,
0,
NULL,
0.0,
0.0
};
#endif
#define VERSION 4000
#define CHIPS_NAME "CHIPS"
#define CHIPS_DRIVER_NAME "chips"
#define CHIPS_MAJOR_VERSION 1
#define CHIPS_MINOR_VERSION 0
#define CHIPS_PATCHLEVEL 0
DriverRec CHIPS = {
VERSION,
CHIPS_DRIVER_NAME,
CHIPSIdentify,
CHIPSProbe,
CHIPSAvailableOptions,
NULL,
0
};
static SymTabRec CHIPSChipsets[] = {
{ CHIPS_CT65520, "ct65520" },
{ CHIPS_CT65525, "ct65525" },
{ CHIPS_CT65530, "ct65530" },
{ CHIPS_CT65535, "ct65535" },
{ CHIPS_CT65540, "ct65540" },
{ CHIPS_CT65545, "ct65545" },
{ CHIPS_CT65546, "ct65546" },
{ CHIPS_CT65548, "ct65548" },
{ CHIPS_CT65550, "ct65550" },
{ CHIPS_CT65554, "ct65554" },
{ CHIPS_CT65555, "ct65555" },
{ CHIPS_CT68554, "ct68554" },
{ CHIPS_CT69000, "ct69000" },
{ CHIPS_CT69030, "ct69030" },
{ CHIPS_CT64200, "ct64200" },
{ CHIPS_CT64300, "ct64300" },
{ -1, NULL }
};
static PciChipsets CHIPSPCIchipsets[] = {
{ CHIPS_CT65545, PCI_CHIP_65545, RES_SHARED_VGA },
{ CHIPS_CT65548, PCI_CHIP_65548, RES_SHARED_VGA },
{ CHIPS_CT65550, PCI_CHIP_65550, RES_SHARED_VGA },
{ CHIPS_CT65554, PCI_CHIP_65554, RES_SHARED_VGA },
{ CHIPS_CT65555, PCI_CHIP_65555, RES_SHARED_VGA },
{ CHIPS_CT68554, PCI_CHIP_68554, RES_SHARED_VGA },
{ CHIPS_CT69000, PCI_CHIP_69000, RES_SHARED_VGA },
{ CHIPS_CT69030, PCI_CHIP_69030, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED}
};
static IsaChipsets CHIPSISAchipsets[] = {
{ CHIPS_CT65520, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65525, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65530, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65535, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65540, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65545, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65546, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65548, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65550, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65554, RES_EXCLUSIVE_VGA },
{ CHIPS_CT65555, RES_EXCLUSIVE_VGA },
{ CHIPS_CT68554, RES_EXCLUSIVE_VGA },
{ CHIPS_CT69000, RES_EXCLUSIVE_VGA },
{ CHIPS_CT69030, RES_EXCLUSIVE_VGA },
{ CHIPS_CT64200, RES_EXCLUSIVE_VGA },
{ CHIPS_CT64300, RES_EXCLUSIVE_VGA },
{ -1, RES_UNDEFINED }
};
typedef enum {
OPTION_LINEAR,
OPTION_NOACCEL,
OPTION_HW_CLKS,
OPTION_SW_CURSOR,
OPTION_HW_CURSOR,
OPTION_STN,
OPTION_USE_MODELINE,
OPTION_LCD_STRETCH,
OPTION_LCD_CENTER,
OPTION_MMIO,
OPTION_FULL_MMIO,
OPTION_SUSPEND_HACK,
OPTION_RGB_BITS,
OPTION_SYNC_ON_GREEN,
OPTION_PANEL_SIZE,
OPTION_18_BIT_BUS,
OPTION_SHOWCACHE,
OPTION_SHADOW_FB,
OPTION_OVERLAY,
OPTION_COLOR_KEY,
OPTION_VIDEO_KEY,
OPTION_FP_CLOCK_8,
OPTION_FP_CLOCK_16,
OPTION_FP_CLOCK_24,
OPTION_FP_CLOCK_32,
OPTION_SET_MCLK,
OPTION_ROTATE,
OPTION_NO_TMED,
OPTION_CRT2_MEM,
OPTION_DUAL_REFRESH,
OPTION_CRT_CLK_INDX,
OPTION_FP_CLK_INDX,
OPTION_FP_MODE
} CHIPSOpts;
static const OptionInfoRec Chips655xxOptions[] = {
{ OPTION_LINEAR, "Linear", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_HW_CLKS, "HWclocks", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_HW_CURSOR, "HWcursor", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_STN, "STN", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_USE_MODELINE, "UseModeline", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_LCD_STRETCH, "NoStretch", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_LCD_CENTER, "LcdCenter", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_MMIO, "MMIO", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SUSPEND_HACK, "SuspendHack", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_PANEL_SIZE, "FixPanelSize", OPTV_BOOLEAN, {0}, FALSE },
#if 0
{ OPTION_RGB_BITS, "RGBbits", OPTV_INTEGER, {0}, FALSE },
#endif
{ OPTION_18_BIT_BUS, "18BitBus", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SHADOW_FB, "ShadowFB", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_SET_MCLK, "SetMclk", OPTV_FREQ, {0}, FALSE },
{ OPTION_FP_CLOCK_8, "FPClock8", OPTV_FREQ, {0}, FALSE },
{ OPTION_FP_CLOCK_16, "FPClock16", OPTV_FREQ, {0}, FALSE },
{ OPTION_FP_CLOCK_24, "FPClock24", OPTV_FREQ, {0}, FALSE },
{ OPTION_FP_MODE, "FPMode", OPTV_BOOLEAN, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
static const OptionInfoRec ChipsWingineOptions[] = {
{ OPTION_LINEAR, "Linear", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_HW_CLKS, "HWclocks", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_HW_CURSOR, "HWcursor", OPTV_BOOLEAN, {0}, FALSE },
#if 0
{ OPTION_RGB_BITS, "RGBbits", OPTV_INTEGER, {0}, FALSE },
#endif
{ OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SHADOW_FB, "ShadowFB", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
static const OptionInfoRec ChipsHiQVOptions[] = {
{ OPTION_LINEAR, "Linear", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_HW_CURSOR, "HWcursor", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_STN, "STN", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_USE_MODELINE, "UseModeline", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_LCD_STRETCH, "NoStretch", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_LCD_CENTER, "LcdCenter", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_MMIO, "MMIO", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_FULL_MMIO, "FullMMIO", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SUSPEND_HACK, "SuspendHack", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_PANEL_SIZE, "FixPanelSize", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_RGB_BITS, "RGBbits", OPTV_INTEGER, {0}, FALSE },
{ OPTION_SYNC_ON_GREEN, "SyncOnGreen", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SHADOW_FB, "ShadowFB", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_OVERLAY, "Overlay", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE },
{ OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
{ OPTION_FP_CLOCK_8, "FPClock8", OPTV_FREQ, {0}, FALSE },
{ OPTION_FP_CLOCK_16, "FPClock16", OPTV_FREQ, {0}, FALSE },
{ OPTION_FP_CLOCK_24, "FPClock24", OPTV_FREQ, {0}, FALSE },
{ OPTION_FP_CLOCK_32, "FPClock32", OPTV_FREQ, {0}, FALSE },
{ OPTION_SET_MCLK, "SetMclk", OPTV_FREQ, {0}, FALSE },
{ OPTION_NO_TMED, "NoTMED", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_CRT2_MEM, "Crt2Memory", OPTV_INTEGER, {0}, FALSE },
{ OPTION_DUAL_REFRESH, "DualRefresh", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_CRT_CLK_INDX, "CrtClkIndx", OPTV_INTEGER, {0}, FALSE },
{ OPTION_FP_CLK_INDX, "FPClkIndx", OPTV_INTEGER, {0}, FALSE },
{ OPTION_FP_MODE, "FPMode", OPTV_BOOLEAN, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
static const char *vgahwSymbols[] = {
"vgaHWAllocDefaultRegs",
"vgaHWFreeHWRec",
"vgaHWGetHWRec",
"vgaHWGetIOBase",
"vgaHWGetIndex",
"vgaHWHBlankKGA",
"vgaHWInit",
"vgaHWLock",
"vgaHWMapMem",
"vgaHWProtect",
"vgaHWRestore",
"vgaHWSave",
"vgaHWUnlock",
"vgaHWVBlankKGA",
"vgaHWddc1SetSpeed",
NULL
};
#ifdef XFree86LOADER
static const char *miscfbSymbols[] = {
"xf1bppScreenInit",
"xf4bppScreenInit",
"cfb8_16ScreenInit",
NULL
};
#endif
static const char *fbSymbols[] = {
"fbScreenInit",
"fbPictureInit",
NULL
};
static const char *xaaSymbols[] = {
"XAACreateInfoRec",
"XAADestroyInfoRec",
"XAAInit",
"XAAInitDualFramebufferOverlay",
"XAAStippleScanlineFuncMSBFirst",
NULL
};
static const char *ramdacSymbols[] = {
"xf86CreateCursorInfoRec",
"xf86DestroyCursorInfoRec",
"xf86InitCursor",
NULL
};
static const char *ddcSymbols[] = {
"xf86DoEDID_DDC1",
"xf86DoEDID_DDC2",
"xf86PrintEDID",
"xf86SetDDCproperties",
NULL
};
static const char *i2cSymbols[] = {
"xf86CreateI2CBusRec",
"xf86I2CBusInit",
"xf86I2CFindBus",
"xf86I2CProbeAddress",
NULL
};
static const char *shadowSymbols[] = {
"ShadowFBInit",
NULL
};
static const char *vbeSymbols[] = {
"VBEInit",
"vbeDoEDID",
"vbeFree",
NULL
};
#ifdef XFree86LOADER
static MODULESETUPPROTO(chipsSetup);
static XF86ModuleVersionInfo chipsVersRec =
{
"chips",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XF86_VERSION_CURRENT,
CHIPS_MAJOR_VERSION, CHIPS_MINOR_VERSION, CHIPS_PATCHLEVEL,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_VIDEODRV,
{0,0,0,0}
};
XF86ModuleData chipsModuleData = { &chipsVersRec, chipsSetup, NULL };
static pointer
chipsSetup(pointer module, pointer opts, int *errmaj, int *errmin)
{
static Bool setupDone = FALSE;
if (!setupDone) {
setupDone = TRUE;
xf86AddDriver(&CHIPS, module, 0);
LoaderRefSymLists(vgahwSymbols, miscfbSymbols, fbSymbols, xaaSymbols,
ramdacSymbols, ddcSymbols, i2cSymbols,
shadowSymbols, vbeSymbols, NULL);
return (pointer)1;
} else {
if (errmaj) *errmaj = LDR_ONCEONLY;
return NULL;
}
}
#endif
static Bool
CHIPSGetRec(ScrnInfoPtr pScrn)
{
if (pScrn->driverPrivate != NULL)
return TRUE;
pScrn->driverPrivate = xnfcalloc(sizeof(CHIPSRec), 1);
if (pScrn->driverPrivate == NULL)
return FALSE;
return TRUE;
}
static void
CHIPSFreeRec(ScrnInfoPtr pScrn)
{
if (pScrn->driverPrivate == NULL)
return;
xfree(pScrn->driverPrivate);
pScrn->driverPrivate = NULL;
}
static void
CHIPSIdentify(int flags)
{
xf86PrintChipsets(CHIPS_NAME, "Driver for Chips and Technologies chipsets",
CHIPSChipsets);
}
static const OptionInfoRec *
CHIPSAvailableOptions(int chipid, int busid)
{
int chip = chipid & 0x0000ffff;
if (busid == BUS_ISA) {
if ((chip == CHIPS_CT64200) || (chip == CHIPS_CT64300))
return ChipsWingineOptions;
}
if (busid == BUS_PCI) {
if ((chip >= CHIPS_CT65550) && (chip <= CHIPS_CT69030))
return ChipsHiQVOptions;
}
return Chips655xxOptions;
}
static Bool
CHIPSProbe(DriverPtr drv, int flags)
{
Bool foundScreen = FALSE;
int numDevSections, numUsed;
GDevPtr *devSections;
int *usedChips;
int i;
if ((numDevSections = xf86MatchDevice(CHIPS_DRIVER_NAME,
&devSections)) <= 0) {
return FALSE;
}
if (xf86GetPciVideoInfo() ) {
numUsed = xf86MatchPciInstances(CHIPS_NAME, PCI_VENDOR_CHIPSTECH,
CHIPSChipsets, CHIPSPCIchipsets,
devSections,numDevSections, drv,
&usedChips);
if (numUsed > 0) {
if (flags & PROBE_DETECT)
foundScreen = TRUE;
else for (i = 0; i < numUsed; i++) {
EntityInfoPtr pEnt;
ScrnInfoPtr pScrn = NULL;
if ((pScrn = xf86ConfigPciEntity(pScrn,0,usedChips[i],
CHIPSPCIchipsets,NULL,
NULL,NULL,NULL,NULL))){
pScrn->driverVersion = VERSION;
pScrn->driverName = CHIPS_DRIVER_NAME;
pScrn->name = CHIPS_NAME;
pScrn->Probe = CHIPSProbe;
pScrn->PreInit = CHIPSPreInit;
pScrn->ScreenInit = CHIPSScreenInit;
pScrn->SwitchMode = CHIPSSwitchMode;
pScrn->AdjustFrame = CHIPSAdjustFrame;
pScrn->EnterVT = CHIPSEnterVT;
pScrn->LeaveVT = CHIPSLeaveVT;
pScrn->FreeScreen = CHIPSFreeScreen;
pScrn->ValidMode = CHIPSValidMode;
foundScreen = TRUE;
}
pEnt = xf86GetEntityInfo(usedChips[i]);
if (pEnt->chipset == CHIPS_CT69030) {
CHIPSEntPtr cPtrEnt = NULL;
DevUnion *pPriv;
xf86SetEntitySharable(usedChips[i]);
if (CHIPSEntityIndex < 0)
CHIPSEntityIndex = xf86AllocateEntityPrivateIndex();
pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex);
if (!pPriv->ptr) {
pPriv->ptr = xnfcalloc(sizeof(CHIPSEntRec), 1);
cPtrEnt = pPriv->ptr;
cPtrEnt->lastInstance = -1;
} else {
cPtrEnt = pPriv->ptr;
}
cPtrEnt->lastInstance++;
xf86SetEntityInstanceForScreen(pScrn, pScrn->entityList[0],
cPtrEnt->lastInstance);
}
}
xfree(usedChips);
}
}
numUsed = xf86MatchIsaInstances(CHIPS_NAME,CHIPSChipsets,CHIPSISAchipsets,
drv,chipsFindIsaDevice,devSections,
numDevSections,&usedChips);
if (numUsed > 0) {
if (flags & PROBE_DETECT)
foundScreen = TRUE;
else for (i = 0; i < numUsed; i++) {
ScrnInfoPtr pScrn = NULL;
if ((pScrn = xf86ConfigIsaEntity(pScrn,0,
usedChips[i],
CHIPSISAchipsets,NULL,
NULL,NULL,NULL,NULL))) {
pScrn->driverVersion = VERSION;
pScrn->driverName = CHIPS_DRIVER_NAME;
pScrn->name = CHIPS_NAME;
pScrn->Probe = CHIPSProbe;
pScrn->PreInit = CHIPSPreInit;
pScrn->ScreenInit = CHIPSScreenInit;
pScrn->SwitchMode = CHIPSSwitchMode;
pScrn->AdjustFrame = CHIPSAdjustFrame;
pScrn->EnterVT = CHIPSEnterVT;
pScrn->LeaveVT = CHIPSLeaveVT;
pScrn->FreeScreen = CHIPSFreeScreen;
pScrn->ValidMode = CHIPSValidMode;
foundScreen = TRUE;
}
xfree(usedChips);
}
}
xfree(devSections);
return foundScreen;
}
static int
chipsFindIsaDevice(GDevPtr dev)
{
int found = -1;
unsigned char tmp;
outb(0x3D6, 0x00);
tmp = inb(0x3D7);
switch (tmp & 0xF0) {
case 0x70:
found = CHIPS_CT65520; break;
case 0x80:
found = CHIPS_CT65530; break;
case 0xA0:
found = CHIPS_CT64200; break;
case 0xB0:
found = CHIPS_CT64300; break;
case 0xC0:
found = CHIPS_CT65535; break;
default:
switch (tmp & 0xF8) {
case 0xD0:
found = CHIPS_CT65540; break;
case 0xD8:
switch (tmp & 7) {
case 3:
found = CHIPS_CT65546; break;
case 4:
found = CHIPS_CT65548; break;
default:
found = CHIPS_CT65545; break;
}
break;
default:
if (tmp == 0x2C) {
outb(0x3D6, 0x01);
tmp = inb(0x3D7);
if (tmp != 0x10) break;
outb(0x3D6, 0x02);
tmp = inb(0x3D7);
switch (tmp) {
case 0xE0:
found = CHIPS_CT65550; break;
case 0xE4:
found = CHIPS_CT65554; break;
case 0xE5:
found = CHIPS_CT65555; break;
case 0xF4:
found = CHIPS_CT68554; break;
case 0xC0:
found = CHIPS_CT69000; break;
case 0x30:
outb(0x3D6, 0x03);
tmp = inb(0x3D7);
if (tmp == 0xC)
found = CHIPS_CT69030;
break;
default:
break;
}
}
break;
}
break;
}
if(found > CHIPS_CT65548) {
outb(0x3D6, 0x08);
tmp = inb(0x3D7);
if(tmp & 0x01) found = -1;
} else if(found > CHIPS_CT65535) {
outb(0x3D6, 0x01);
tmp = inb(0x3D7);
if ((tmp & 0x07) == 0x06) found = -1;
}
return found;
}
Bool
CHIPSPreInit(ScrnInfoPtr pScrn, int flags)
{
pciVideoPtr pciPtr;
ClockRangePtr clockRanges;
int i;
CHIPSPtr cPtr;
Bool res = FALSE;
CHIPSEntPtr cPtrEnt = NULL;
if (flags & PROBE_DETECT) return FALSE;
if (!xf86LoadSubModule(pScrn, "vgahw"))
return FALSE;
xf86LoaderReqSymLists(vgahwSymbols, NULL);
if (!CHIPSGetRec(pScrn)) {
return FALSE;
}
cPtr = CHIPSPTR(pScrn);
if (pScrn->numEntities != 1)
return FALSE;
for (i = 0; i<pScrn->numEntities; i++) {
cPtr->pEnt = xf86GetEntityInfo(pScrn->entityList[i]);
if (cPtr->pEnt->resources) return FALSE;
cPtr->Chipset = cPtr->pEnt->chipset;
pScrn->chipset = (char *)xf86TokenToString(CHIPSChipsets,
cPtr->pEnt->chipset);
if ((cPtr->Chipset == CHIPS_CT64200) ||
(cPtr->Chipset == CHIPS_CT64300)) cPtr->Flags |= ChipsWingine;
if ((cPtr->Chipset >= CHIPS_CT65550) &&
(cPtr->Chipset <= CHIPS_CT69030)) cPtr->Flags |= ChipsHiQV;
if (cPtr->pEnt->location.type == BUS_PCI) {
pciPtr = xf86GetPciInfoForEntity(cPtr->pEnt->index);
cPtr->PciInfo = pciPtr;
cPtr->PciTag = pciTag(cPtr->PciInfo->bus,
cPtr->PciInfo->device,
cPtr->PciInfo->func);
}
}
#if 0
if (xf86LoadSubModule(pScrn, "int10")) {
xf86Int10InfoPtr pInt;
xf86LoaderReqSymLists(int10Symbols, NULL);
#if 1
xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n");
pInt = xf86InitInt10(cPtr->pEnt->index);
xf86FreeInt10(pInt);
#endif
}
#endif
if (xf86LoadSubModule(pScrn, "vbe")) {
xf86LoaderReqSymLists(vbeSymbols, NULL);
cPtr->pVbe = VBEInit(NULL,cPtr->pEnt->index);
}
switch (cPtr->Chipset) {
case CHIPS_CT69030:
cPtr->Flags |= ChipsDualChannelSupport;
case CHIPS_CT69000:
cPtr->Flags |= ChipsFullMMIOSupport;
case CHIPS_CT65555:
cPtr->Flags |= ChipsImageReadSupport;
case CHIPS_CT68554:
cPtr->Flags |= ChipsTMEDSupport;
case CHIPS_CT65554:
case CHIPS_CT65550:
cPtr->Flags |= ChipsGammaSupport;
cPtr->Flags |= ChipsVideoSupport;
case CHIPS_CT65548:
case CHIPS_CT65546:
case CHIPS_CT65545:
cPtr->Flags |= ChipsMMIOSupport;
case CHIPS_CT64300:
cPtr->Flags |= ChipsAccelSupport;
case CHIPS_CT65540:
cPtr->Flags |= ChipsHDepthSupport;
cPtr->Flags |= ChipsDPMSSupport;
case CHIPS_CT65535:
case CHIPS_CT65530:
case CHIPS_CT65525:
cPtr->Flags |= ChipsLinearSupport;
case CHIPS_CT64200:
case CHIPS_CT65520:
break;
}
if (xf86IsEntityShared(pScrn->entityList[0])) {
if (!(cPtr->Flags & ChipsDualChannelSupport))
return FALSE;
if (cPtr->pEnt->location.type != BUS_PCI)
return FALSE;
if (xf86IsEntityShared(pScrn->entityList[0])) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
cPtr->entityPrivate = cPtrEnt;
}
#if 0
cPtr->device = xf86GetDevFromEntity(pScrn->entityList[0],
pScrn->entityInstanceList[0]);
#endif
}
CHIPSSetStdExtFuncs(cPtr);
if (IS_HiQV(cPtr))
res = chipsPreInitHiQV(pScrn, flags);
else if (IS_Wingine(cPtr))
res = chipsPreInitWingine(pScrn, flags);
else
res = chipsPreInit655xx(pScrn, flags);
if (cPtr->UseFullMMIO)
chipsUnmapMem(pScrn);
if (!res) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
return FALSE;
}
clockRanges = xnfcalloc(sizeof(ClockRange), 1);
clockRanges->next = NULL;
clockRanges->ClockMulFactor = cPtr->ClockMulFactor;
clockRanges->minClock = cPtr->MinClock;
clockRanges->maxClock = cPtr->MaxClock;
clockRanges->clockIndex = -1;
if (cPtr->PanelType & ChipsLCD) {
clockRanges->interlaceAllowed = FALSE;
clockRanges->doubleScanAllowed = FALSE;
} else {
clockRanges->interlaceAllowed = TRUE;
clockRanges->doubleScanAllowed = TRUE;
}
pScrn->videoRam -= (cPtr->FrameBufferSize + 1023) / 1024;
cPtr->Rounding = 8 * (pScrn->bitsPerPixel <= 8 ? 8
: pScrn->bitsPerPixel);
i = xf86ValidateModes(pScrn, pScrn->monitor->Modes,
pScrn->display->modes, clockRanges,
NULL, 256, 2048, cPtr->Rounding,
128, 2048, pScrn->display->virtualX,
pScrn->display->virtualY, cPtr->FbMapSize,
LOOKUP_BEST_REFRESH);
if (i == -1) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
pScrn->videoRam += (cPtr->FrameBufferSize + 1023) / 1024;
xf86PruneDriverModes(pScrn);
if (i == 0 || pScrn->modes == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes found\n");
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86SetCrtcForModes(pScrn, INTERLACE_HALVE_V);
pScrn->currentMode = pScrn->modes;
xf86PrintModes(pScrn);
xf86SetDpi(pScrn, 0, 0);
switch (pScrn->bitsPerPixel) {
case 1:
if (xf86LoadSubModule(pScrn, "xf1bpp") == NULL) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86LoaderReqSymbols("xf1bppScreenInit", NULL);
break;
case 4:
if (xf86LoadSubModule(pScrn, "xf4bpp") == NULL) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86LoaderReqSymbols("xf4bppScreenInit", NULL);
break;
case 16:
if (cPtr->Flags & ChipsOverlay8plus16) {
if (xf86LoadSubModule(pScrn, "xf8_16bpp") == NULL) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86LoaderReqSymbols("cfb8_16bppScreenInit", NULL);
break;
}
default:
if (xf86LoadSubModule(pScrn, "fb") == NULL) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86LoaderReqSymLists(fbSymbols, NULL);
break;
}
if (cPtr->Flags & ChipsAccelSupport) {
if (!xf86LoadSubModule(pScrn, "xaa")) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86LoaderReqSymLists(xaaSymbols, NULL);
}
if (cPtr->Flags & ChipsShadowFB) {
if (!xf86LoadSubModule(pScrn, "shadowfb")) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86LoaderReqSymLists(shadowSymbols, NULL);
}
if (cPtr->Accel.UseHWCursor) {
if (!xf86LoadSubModule(pScrn, "ramdac")) {
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
CHIPSFreeRec(pScrn);
return FALSE;
}
xf86LoaderReqSymLists(ramdacSymbols, NULL);
}
if (cPtr->Flags & ChipsLinearSupport)
xf86SetOperatingState(resVgaMem, cPtr->pEnt->index, ResDisableOpr);
if (cPtr->MMIOBaseVGA)
xf86SetOperatingState(resVgaIo, cPtr->pEnt->index, ResDisableOpr);
vbeFree(cPtr->pVbe);
cPtr->pVbe = NULL;
return TRUE;
}
static Bool
chipsPreInitHiQV(ScrnInfoPtr pScrn, int flags)
{
int bytesPerPixel;
unsigned char tmp;
MessageType from;
int i;
unsigned int Probed[3], FPclkI, CRTclkI;
double real;
int val, indx;
const char *s;
pointer pVbeModule = NULL;
vgaHWPtr hwp;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSEntPtr cPtrEnt = NULL;
CHIPSPanelSizePtr Size = &cPtr->PanelSize;
CHIPSMemClockPtr MemClk = &cPtr->MemClock;
CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
resRange linearRes[] = { {ResExcMemBlock|ResBios|ResBus,0,0},_END };
pScrn->monitor = pScrn->confScreen->monitor;
if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support24bppFb | Support32bppFb |
SupportConvert32to24 | PreferConvert32to24))
return FALSE;
else {
switch (pScrn->depth) {
case 1:
case 4:
case 8:
case 15:
case 16:
case 24:
case 32:
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Given depth (%d) is not supported by this driver\n",
pScrn->depth);
return FALSE;
}
}
xf86PrintDepthBpp(pScrn);
if (pScrn->depth == 24 && pix24bpp == 0)
pix24bpp = xf86GetBppFromDepth(pScrn, 24);
if (!vgaHWGetHWRec(pScrn))
return FALSE;
hwp = VGAHWPTR(pScrn);
vgaHWGetIOBase(hwp);
cPtr->PIOBase = hwp->PIOOffset;
if ((cPtr->Flags & ChipsDualChannelSupport) &&
(! xf86IsEntityShared(pScrn->entityList[0])))
vgaHWAllocDefaultRegs(&(cPtr->VgaSavedReg2));
if (pScrn->depth > 8) {
rgb zeros = {0, 0, 0};
if (!xf86SetWeight(pScrn, zeros, zeros)) {
return FALSE;
} else {
;
}
}
if (!xf86SetDefaultVisual(pScrn, -1))
return FALSE;
if (pScrn->depth > 1) {
Gamma zeros = {0.0, 0.0, 0.0};
if (!xf86SetGamma(pScrn, zeros))
return FALSE;
}
bytesPerPixel = max(1, pScrn->bitsPerPixel >> 3);
xf86CollectOptions(pScrn, NULL);
if (!(cPtr->Options = xalloc(sizeof(ChipsHiQVOptions))))
return FALSE;
memcpy(cPtr->Options, ChipsHiQVOptions, sizeof(ChipsHiQVOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, cPtr->Options);
if (pScrn->depth > 1) {
pScrn->rgbBits = 8;
if (xf86GetOptValInteger(cPtr->Options, OPTION_RGB_BITS, &val)) {
if (val == 6 || val == 8) {
pScrn->rgbBits = val;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Bits per RGB set to "
"%d\n", pScrn->rgbBits);
} else
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid number of "
"rgb bits %d\n", val);
}
}
if ((cPtr->Flags & ChipsAccelSupport) &&
(xf86ReturnOptValBool(cPtr->Options, OPTION_NOACCEL, FALSE))) {
cPtr->Flags &= ~ChipsAccelSupport;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Acceleration disabled\n");
}
from = X_DEFAULT;
if (pScrn->bitsPerPixel < 8) {
cPtr->Accel.UseHWCursor = FALSE;
} else {
cPtr->Accel.UseHWCursor = TRUE;
}
if (xf86GetOptValBool(cPtr->Options, OPTION_HW_CURSOR,
&cPtr->Accel.UseHWCursor))
from = X_CONFIG;
if (xf86GetOptValBool(cPtr->Options, OPTION_SW_CURSOR,
&cPtr->Accel.UseHWCursor)) {
from = X_CONFIG;
cPtr->Accel.UseHWCursor = !cPtr->Accel.UseHWCursor;
}
xf86DrvMsg(pScrn->scrnIndex, from, "Using %s cursor\n",
(cPtr->Accel.UseHWCursor) ? "HW" : "SW");
if (pScrn->bitsPerPixel < 8) {
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE)) {
cPtr->Flags &= ~ChipsLinearSupport;
from = X_CONFIG;
}
} else if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, TRUE)) {
cPtr->Flags &= ~ChipsLinearSupport;
from = X_CONFIG;
}
if (cPtr->Flags & ChipsLinearSupport) {
if (cPtr->pEnt->location.type == BUS_PCI) {
#if X_BYTE_ORDER == X_BIG_ENDIAN
cPtr->FbAddress = (cPtr->PciInfo->memBase[0] & 0xff800000) + 0x800000L;
#else
cPtr->FbAddress = cPtr->PciInfo->memBase[0] & 0xff800000;
#endif
from = X_PROBED;
if (xf86RegisterResources(cPtr->pEnt->index,NULL,ResNone))
cPtr->Flags &= ~ChipsLinearSupport;
} else {
if (cPtr->pEnt->device->MemBase) {
cPtr->FbAddress = cPtr->pEnt->device->MemBase;
from = X_CONFIG;
} else {
cPtr->FbAddress = ((unsigned int)
(cPtr->readXR(cPtr, 0x06))) << 24;
cPtr->FbAddress |= ((unsigned int)
(0x80 & (cPtr->readXR(cPtr, 0x05)))) << 16;
from = X_PROBED;
}
linearRes[0].rBegin = cPtr->FbAddress;
linearRes[0].rEnd = cPtr->FbAddress + 0x800000;
if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
cPtr->Flags &= ~ChipsLinearSupport;
from = X_PROBED;
}
}
}
if (cPtr->Flags & ChipsLinearSupport) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Enabling linear addressing\n");
xf86DrvMsg(pScrn->scrnIndex, from,
"base address is set at 0x%lX.\n", cPtr->FbAddress);
cPtr->IOAddress = cPtr->FbAddress + 0x400000L;
} else
xf86DrvMsg(pScrn->scrnIndex, from,
"Disabling linear addressing\n");
if ((s = xf86GetOptValString(cPtr->Options, OPTION_ROTATE))
|| xf86ReturnOptValBool(cPtr->Options, OPTION_SHADOW_FB, FALSE)) {
if (!(cPtr->Flags & ChipsLinearSupport)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Option \"ShadowFB\" ignored. Not supported without linear addressing\n");
} else if (pScrn->depth < 8) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Option \"ShadowFB\" ignored. Not supported at this depth.\n");
} else {
cPtr->Rotate = 0;
if (s) {
if(!xf86NameCmp(s, "CW")) {
cPtr->Flags |= ChipsShadowFB;
cPtr->Rotate = 1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Rotating screen clockwise\n");
} else if(!xf86NameCmp(s, "CCW")) {
cPtr->Flags |= ChipsShadowFB;
cPtr->Rotate = -1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rotating screen"
"counter clockwise\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "\"%s\" is not a valid"
"value for Option \"Rotate\"\n", s);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Valid options are \"CW\" or \"CCW\"\n");
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using \"Shadow Framebuffer\"\n");
cPtr->Flags |= ChipsShadowFB;
}
}
}
if ((s = xf86GetOptValString(cPtr->Options, OPTION_OVERLAY))) {
if (!*s || !xf86NameCmp(s, "8,16") || !xf86NameCmp(s, "16,8")) {
if (pScrn->bitsPerPixel == 16) {
if (cPtr->Flags & ChipsLinearSupport) {
cPtr->Flags |= ChipsOverlay8plus16;
if(!xf86GetOptValInteger(
cPtr->Options, OPTION_COLOR_KEY, &(pScrn->colorKey)))
pScrn->colorKey = TRANSPARENCY_KEY;
pScrn->overlayFlags = OVERLAY_8_16_DUALFB;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"PseudoColor overlay enabled.\n");
if (!xf86IsOptionSet(cPtr->Options, OPTION_LCD_STRETCH))
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" - Forcing option \"NoStretch\".\n");
if (!xf86IsOptionSet(cPtr->Options, OPTION_LCD_CENTER))
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" - Forcing option \"LcdCenter\".\n");
if (cPtr->Flags & ChipsShadowFB) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" - Disabling \"Shadow Framebuffer\".\n");
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" Not support with option \"8Plus16\".\n");
cPtr->Flags &= ~ChipsShadowFB;
cPtr->Rotate = 0;
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Option \"Overlay\" ignored. Not supported without linear addressing\n");
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Option \"Overlay\" is not supported in this configuration\n");
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"\"%s\" is not a valid value for Option \"Overlay\"\n", s);
}
}
if (!(cPtr->Flags & ChipsOverlay8plus16)) {
if(xf86GetOptValInteger(cPtr->Options, OPTION_VIDEO_KEY,
&(cPtr->videoKey))) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n",
cPtr->videoKey);
} else {
cPtr->videoKey = (1 << pScrn->offset.red) |
(1 << pScrn->offset.green) |
(((pScrn->mask.blue >> pScrn->offset.blue) - 1)
<< pScrn->offset.blue);
}
}
if (cPtr->Flags & ChipsShadowFB) {
if (cPtr->Flags & ChipsAccelSupport) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"HW acceleration is not supported with shadow fb\n");
cPtr->Flags &= ~ChipsAccelSupport;
}
if (cPtr->Rotate && cPtr->Accel.UseHWCursor) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"HW cursor is not supported with rotate\n");
cPtr->Accel.UseHWCursor = FALSE;
}
}
if (xf86ReturnOptValBool(cPtr->Options, OPTION_MMIO, TRUE)) {
cPtr->UseMMIO = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using MMIO\n");
if (xf86ReturnOptValBool(cPtr->Options, OPTION_FULL_MMIO, FALSE)) {
if ((cPtr->Flags & ChipsLinearSupport)
&& (cPtr->Flags & ChipsFullMMIOSupport)
&& (cPtr->pEnt->location.type == BUS_PCI)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Enabling Full MMIO\n");
cPtr->UseFullMMIO = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using Full MMIO\n");
cPtr->FbMapSize = 1024 * 1024;
if (!chipsMapMem(pScrn))
return FALSE;
if (cPtr->MMIOBaseVGA) {
CHIPSSetMmioExtFuncs(cPtr);
CHIPSHWSetMmioFuncs(pScrn, cPtr->MMIOBaseVGA, 0x0);
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"FULL_MMIO option ignored\n");
}
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,"Disabling MMIO: "
"no acceleration, no hw_cursor\n");
cPtr->UseMMIO = FALSE;
cPtr->Accel.UseHWCursor = FALSE;
cPtr->Flags &= ~ChipsAccelSupport;
}
if (cPtr->Flags & ChipsDualChannelSupport) {
if (xf86IsEntityShared(pScrn->entityList[0])) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
#if 1
if (xf86IsPrimInitDone(pScrn->entityList[0]))
#else
if (cPtr->pEnt->device->screen == 1)
#endif
{
cPtr->SecondCrtc = TRUE;
cPtr->UseDualChannel = TRUE;
} else
cPtr->SecondCrtc = FALSE;
} else {
if (xf86ReturnOptValBool(cPtr->Options,
OPTION_DUAL_REFRESH, FALSE)) {
cPtr->Flags |= ChipsDualRefresh;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Dual Refresh mode enabled\n");
cPtr->UseDualChannel = TRUE;
}
}
cPtr->storeIOSS = cPtr->readIOSS(cPtr);
cPtr->storeMSS = cPtr->readMSS(cPtr);
DUALOPEN;
}
if (cPtr->pEnt->device->videoRam != 0) {
pScrn->videoRam = cPtr->pEnt->device->videoRam;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "VideoRAM: %d kByte\n",
pScrn->videoRam);
} else {
switch (cPtr->Chipset) {
case CHIPS_CT69030:
pScrn->videoRam = 4096;
cPtr->Flags |= Chips64BitMemory;
break;
case CHIPS_CT69000:
pScrn->videoRam = 2048;
cPtr->Flags |= Chips64BitMemory;
break;
case CHIPS_CT65550:
switch (((cPtr->readXR(cPtr, 0x43)) & 0x06) >> 1) {
case 0:
pScrn->videoRam = 1024;
break;
case 1:
case 2:
case 3:
pScrn->videoRam = 2048;
break;
}
break;
default:
tmp = (cPtr->readXR(cPtr, 0xE0)) & 0xF;
switch (tmp) {
case 0:
pScrn->videoRam = 512;
break;
case 1:
pScrn->videoRam = 1024;
break;
case 2:
pScrn->videoRam = 1536;
break;
case 3:
pScrn->videoRam = 2048;
break;
case 7:
pScrn->videoRam = 4096;
break;
default:
pScrn->videoRam = 1024;
break;
}
tmp = cPtr->readXR(cPtr, 0x43);
if ((tmp & 0x10) == 0x10)
cPtr->Flags |= Chips64BitMemory;
break;
}
}
if ((cPtr->Flags & ChipsDualChannelSupport) &&
(xf86IsEntityShared(pScrn->entityList[0]))) {
if(cPtr->SecondCrtc == FALSE) {
int crt2mem = -1, adjust;
xf86GetOptValInteger(cPtr->Options, OPTION_CRT2_MEM, &crt2mem);
if (crt2mem > 0) {
adjust = crt2mem;
from = X_CONFIG;
} else {
adjust = pScrn->videoRam / 2;
from = X_DEFAULT;
}
xf86DrvMsg(pScrn->scrnIndex, from,
"CRT2 will use %dK of VideoRam\n",
adjust);
cPtrEnt->mastervideoRam = pScrn->videoRam - adjust;
pScrn->videoRam = cPtrEnt->mastervideoRam;
cPtrEnt->slavevideoRam = adjust;
cPtrEnt->masterFbAddress = cPtr->FbAddress;
cPtr->FbMapSize =
cPtrEnt->masterFbMapSize = pScrn->videoRam * 1024;
cPtrEnt->slaveFbMapSize = cPtrEnt->slavevideoRam * 1024;
} else {
cPtrEnt->slaveFbAddress = cPtr->FbAddress +
cPtrEnt->masterFbAddress;
cPtr->FbMapSize = cPtrEnt->slaveFbMapSize;
pScrn->videoRam = cPtrEnt->slavevideoRam;
}
cPtrEnt->refCount++;
} else {
cPtr->FbMapSize = pScrn->videoRam * 1024;
}
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VideoRAM: %d kByte\n",
pScrn->videoRam);
cPtr->SuspendHack.vgaIOBaseFlag = ((hwp->readMiscOut(hwp)) & 0x01);
cPtr->IOBase = (unsigned int)(cPtr->SuspendHack.vgaIOBaseFlag ?
0x3D0 : 0x3B0);
if ((pVbeModule = xf86LoadSubModule(pScrn, "ddc"))) {
Bool ddc_done = FALSE;
xf86MonPtr pMon;
xf86LoaderReqSymLists(ddcSymbols, NULL);
if (cPtr->pVbe) {
if ((pMon
= xf86PrintEDID(vbeDoEDID(cPtr->pVbe, pVbeModule))) != NULL) {
ddc_done = TRUE;
xf86SetDDCproperties(pScrn,pMon);
}
}
if (!ddc_done)
if (xf86LoadSubModule(pScrn, "i2c")) {
xf86LoaderReqSymLists(i2cSymbols,NULL);
if (chips_i2cInit(pScrn)) {
if ((pMon = xf86PrintEDID(xf86DoEDID_DDC2(pScrn->scrnIndex,
cPtr->I2C))) != NULL)
ddc_done = TRUE;
xf86SetDDCproperties(pScrn,pMon);
}
}
if (!ddc_done)
chips_ddc1(pScrn);
}
tmp = cPtr->readFR(cPtr, 0x10);
switch (tmp & 0x3) {
case 0:
if (xf86ReturnOptValBool(cPtr->Options, OPTION_STN, FALSE)) {
cPtr->PanelType |= ChipsSS;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "SS-STN probed\n");
} else {
cPtr->PanelType |= ChipsTFT;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "TFT probed\n");
}
break;
case 2:
cPtr->PanelType |= ChipsDS;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DS-STN probed\n");
case 3:
cPtr->PanelType |= ChipsDD;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DD-STN probed\n");
break;
default:
break;
}
chipsSetPanelType(cPtr);
from = X_PROBED;
{
Bool fp_mode;
if (xf86GetOptValBool(cPtr->Options, OPTION_FP_MODE, &fp_mode)) {
if (fp_mode) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing FP Mode on\n");
cPtr->PanelType |= ChipsLCD;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing FP Mode off\n");
cPtr->PanelType = ~ChipsLCD;
}
from = X_CONFIG;
}
}
if ((cPtr->PanelType & ChipsLCD) && (cPtr->PanelType & ChipsCRT))
xf86DrvMsg(pScrn->scrnIndex, from, "LCD/CRT\n");
else if (cPtr->PanelType & ChipsLCD)
xf86DrvMsg(pScrn->scrnIndex, from, "LCD\n");
else if (cPtr->PanelType & ChipsCRT) {
xf86DrvMsg(pScrn->scrnIndex, from, "CRT\n");
#if 1
cPtr->Monitor = chipsSetMonitor(pScrn);
#endif
}
if (cPtr->PanelType & ChipsLCD) {
unsigned char fr25, tmp1;
#ifdef DEBUG
unsigned char fr26;
char tmp2;
#endif
fr25 = cPtr->readFR(cPtr, 0x25);
tmp = cPtr->readFR(cPtr, 0x20);
Size->HDisplay = ((tmp + ((fr25 & 0x0F) << 8)) + 1) << 3;
tmp = cPtr->readFR(cPtr, 0x30);
tmp1 = cPtr->readFR(cPtr, 0x35);
Size->VDisplay = ((tmp1 & 0x0F) << 8) + tmp + 1;
#ifdef DEBUG
tmp = cPtr->readFR(cPtr, 0x21);
Size->HRetraceStart = ((tmp + ((fr25 & 0xF0) << 4)) + 1) << 3;
tmp1 = cPtr->readFR(cPtr, 0x22);
tmp2 = (tmp1 & 0x1F) - (tmp & 0x3F);
Size->HRetraceEnd = ((((tmp2 < 0) ? (tmp2 + 0x40) : tmp2) << 3)
+ Size->HRetraceStart);
tmp = cPtr->readFR(cPtr, 0x23);
fr26 = cPtr->readFR(cPtr, 0x26);
Size->HTotal = ((tmp + ((fr26 & 0x0F) << 8)) + 5) << 3;
xf86ErrorF("x=%i, y=%i; xSync=%i, xSyncEnd=%i, xTotal=%i\n",
Size->HDisplay, Size->VDisplay,
Size->HRetraceStart,Size->HRetraceEnd,
Size->HTotal);
#endif
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Display Size: x=%i; y=%i\n",
Size->HDisplay, Size->VDisplay);
if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Display size overridden by modelines.\n");
}
}
if (IS_STN(cPtr->PanelType)) {
tmp = cPtr->readFR(cPtr, 0x1A);
if (tmp & 1) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Frame Buffer used\n");
if (!(tmp & 0x80)) {
cPtr->FrameBufferSize = ( Size->HDisplay *
Size->VDisplay / 5 ) * ((tmp & 2) ? 1 : 2);
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Using embedded Frame Buffer, size %d bytes\n",
cPtr->FrameBufferSize);
} else
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Using external Frame Buffer used\n");
}
if (tmp & 2)
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Frame accelerator enabled\n");
}
tmp = (cPtr->readXR(cPtr, 0x08)) & 1;
if (tmp == 1) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "PCI Bus\n");
cPtr->Bus = ChipsPCI;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VL Bus\n");
cPtr->Bus = ChipsVLB;
}
if (pScrn->bitsPerPixel < 8) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Disabling acceleration for %d bpp\n", pScrn->bitsPerPixel);
cPtr->Flags &= ~ChipsAccelSupport;
}
if ((pScrn->bitsPerPixel == 8) || ((cPtr->Chipset >= CHIPS_CT65555) &&
(pScrn->bitsPerPixel >= 8) && (pScrn->bitsPerPixel <= 24)))
cPtr->Flags |= ChipsColorTransparency;
else
cPtr->Flags &= ~ChipsColorTransparency;
if (!((cPtr->readXR(cPtr, 0xD0)) & 0x01))
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Internal DAC disabled\n");
cPtr->Regs32 = ChipsReg32HiQV;
cPtr->SyncResetIgn = TRUE;
pScrn->numClocks = 26;
pScrn->progClock = TRUE;
cPtr->ClockType = HiQV_STYLE | TYPE_PROGRAMMABLE;
if (cPtr->pEnt->device->textClockFreq > 0) {
SaveClk->Clock = cPtr->pEnt->device->textClockFreq;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using textclock freq: %7.3f.\n",
SaveClk->Clock/1000.0);
} else
SaveClk->Clock = 0;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Using programmable clocks\n");
switch (cPtr->Chipset) {
case CHIPS_CT65550:
if (((cPtr->readXR(cPtr, 0x04)) & 0xF) < 6)
MemClk->Max = 38000;
else
MemClk->Max = 50000;
break;
case CHIPS_CT65554:
case CHIPS_CT65555:
case CHIPS_CT68554:
MemClk->Max = 55000;
break;
case CHIPS_CT69000:
MemClk->Max = 83000;
break;
case CHIPS_CT69030:
MemClk->Max = 100000;
break;
}
for (i = 0; i < 3; i++) {
unsigned int N,M,PSN,P,VCO_D;
int offset = i * 4;
tmp = cPtr->readXR(cPtr,0xC2 + offset);
M = (cPtr->readXR(cPtr, 0xC0 + offset)
| (tmp & 0x03)) + 2;
N = (cPtr->readXR(cPtr, 0xC1 + offset)
| (( tmp >> 4) & 0x03)) + 2;
tmp = cPtr->readXR(cPtr, 0xC3 + offset);
PSN = (cPtr->Chipset == CHIPS_CT69000 || cPtr->Chipset == CHIPS_CT69030)
? 1 : (((tmp & 0x1) ? 1 : 4) * ((tmp & 0x02) ? 5 : 1));
VCO_D = ((tmp & 0x04) ? ((cPtr->Chipset == CHIPS_CT69000 ||
cPtr->Chipset == CHIPS_CT69030) ? 1 : 16) : 4);
P = ((tmp & 0x70) >> 4);
Probed[i] = VCO_D * Fref / N;
Probed[i] = Probed[i] * M / (PSN * (1 << P));
Probed[i] = Probed[i] / 1000;
}
CRTclkI = (hwp->readMiscOut(hwp) >> 2) & 0x03;
if (CRTclkI == 3) CRTclkI = 2;
if (cPtr->Chipset == CHIPS_CT69030)
FPclkI = (cPtr->readFR(cPtr, 0x01) >> 2) & 0x3;
else
FPclkI = (cPtr->readFR(cPtr, 0x03) >> 2) & 0x3;
if (FPclkI == 3) FPclkI = 2;
for (i = 0; i < 3; i++) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Dot clock %i: %7.3f MHz",i,
(float)(Probed[i])/1000.);
if (FPclkI == i) xf86ErrorF(" FPclk");
if (CRTclkI == i) xf86ErrorF(" CRTclk");
xf86ErrorF("\n");
}
cPtr->FPclock = Probed[FPclkI];
cPtr->FPclkInx = FPclkI;
if (CRTclkI == FPclkI) {
if (FPclkI == 2)
CRTclkI = 1;
else
CRTclkI = 2;
}
cPtr->CRTclkInx = CRTclkI;
if (xf86GetOptValInteger(cPtr->Options, OPTION_CRT_CLK_INDX, &indx)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Force CRT Clock index to %d\n",
indx);
cPtr->CRTclkInx = indx;
if (xf86GetOptValInteger(cPtr->Options, OPTION_FP_CLK_INDX, &indx)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Force FP Clock index to %d\n", indx);
cPtr->FPclkInx = indx;
} else {
if (indx == cPtr->FPclkInx) {
if (indx == 2)
cPtr->FPclkInx = 1;
else
cPtr->FPclkInx = indx + 1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"FP Clock index forced to %d\n", cPtr->FPclkInx);
}
}
} else if (xf86GetOptValInteger(cPtr->Options, OPTION_FP_CLK_INDX,
&indx)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Force FP Clock index to %d\n", indx);
cPtr->FPclkInx = indx;
if (indx == cPtr->CRTclkInx) {
if (indx == 2)
cPtr->CRTclkInx = 1;
else
cPtr->CRTclkInx = indx + 1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"CRT Clock index forced to %d\n", cPtr->CRTclkInx);
}
}
MemClk->xrCC = cPtr->readXR(cPtr, 0xCC);
MemClk->M = (MemClk->xrCC & 0x7F) + 2;
MemClk->xrCD = cPtr->readXR(cPtr, 0xCD);
MemClk->N = (MemClk->xrCD & 0x7F) + 2;
MemClk->xrCE = cPtr->readXR(cPtr, 0xCE);
MemClk->PSN = (MemClk->xrCE & 0x1) ? 1 : 4;
MemClk->P = ((MemClk->xrCE & 0x70) >> 4);
MemClk->ProbedClk = 4 * Fref / MemClk->N;
MemClk->ProbedClk = MemClk->ProbedClk * MemClk->M / (MemClk->PSN *
(1 << MemClk->P));
MemClk->ProbedClk = MemClk->ProbedClk / 1000;
MemClk->Clk = MemClk->ProbedClk;
if (xf86GetOptValFreq(cPtr->Options, OPTION_SET_MCLK, OPTUNITS_MHZ, &real)) {
int mclk = (int)(real * 1000.0);
if (mclk <= MemClk->Max) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using memory clock of %7.3f MHz\n",
(float)(mclk/1000.));
if (abs(mclk - MemClk->ProbedClk) > 50) {
unsigned char vclk[3];
MemClk->Clk = mclk;
chipsCalcClock(pScrn, MemClk->Clk, vclk);
MemClk->M = vclk[1] + 2;
MemClk->N = vclk[2] + 2;
MemClk->P = (vclk[0] & 0x70) >> 4;
MemClk->PSN = (vclk[0] & 0x1) ? 1 : 4;
MemClk->xrCC = vclk[1];
MemClk->xrCD = vclk[2];
MemClk->xrCE = 0x80 || vclk[0];
}
} else
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Memory clock of %7.3f MHz exceeds limit of %7.3f MHz\n",
(float)(mclk/1000.),
(float)(MemClk->Max/1000.));
} else
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Probed memory clock of %7.3f MHz\n",
(float)(MemClk->ProbedClk/1000.));
cPtr->ClockMulFactor = 1;
cPtr->MinClock = 11000;
xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %7.3f MHz\n",
(float)(cPtr->MinClock / 1000.));
switch (cPtr->Chipset) {
case CHIPS_CT69030:
cPtr->MaxClock = 170000;
break;
case CHIPS_CT69000:
cPtr->MaxClock = 135000;
break;
case CHIPS_CT68554:
case CHIPS_CT65555:
cPtr->MaxClock = 110000;
break;
case CHIPS_CT65554:
cPtr->MaxClock = 95000;
break;
case CHIPS_CT65550:
if (((cPtr->readXR(cPtr, 0x04)) & 0xF) < 6) {
if ((cPtr->readFR(cPtr, 0x0A)) & 2) {
cPtr->MaxClock = 100000;
} else {
cPtr->MaxClock = 80000;
}
} else
cPtr->MaxClock = 95000;
break;
}
if (cPtr->Flags & Chips64BitMemory) {
if (cPtr->FrameBufferSize && (cPtr->PanelType & ChipsLCD))
if (cPtr->Flags & ChipsOverlay8plus16 )
cPtr->MaxClock = min(cPtr->MaxClock, MemClk->Clk * 8 * 0.7 / 4);
else
cPtr->MaxClock = min(cPtr->MaxClock,
MemClk->Clk * 8 * 0.7 / (bytesPerPixel + 1));
else
if (cPtr->Flags & ChipsOverlay8plus16)
cPtr->MaxClock = min(cPtr->MaxClock, MemClk->Clk * 8 * 0.7 / 3);
else
cPtr->MaxClock = min(cPtr->MaxClock,
MemClk->Clk * 8 * 0.7 / bytesPerPixel);
} else {
if (cPtr->FrameBufferSize && (cPtr->PanelType & ChipsLCD))
if (cPtr->Flags & ChipsOverlay8plus16 )
cPtr->MaxClock = min(cPtr->MaxClock, MemClk->Clk * 4 * 0.7 / 4);
else
cPtr->MaxClock = min(cPtr->MaxClock,
MemClk->Clk * 4 * 0.7 / (bytesPerPixel + 1));
else
if (cPtr->Flags & ChipsOverlay8plus16)
cPtr->MaxClock = min(cPtr->MaxClock, MemClk->Clk * 4 * 0.7 / 3);
else
cPtr->MaxClock = min(cPtr->MaxClock,
MemClk->Clk * 4 * 0.7 / bytesPerPixel);
}
if (cPtr->pEnt->device->dacSpeeds[0]) {
int speed = 0;
switch (pScrn->bitsPerPixel) {
case 1:
case 4:
case 8:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP8];
break;
case 16:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP16];
break;
case 24:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP24];
break;
case 32:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP32];
break;
}
if (speed == 0)
speed = cPtr->pEnt->device->dacSpeeds[0];
from = X_CONFIG;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"User max pixel clock of %7.3f MHz overrides %7.3f MHz limit\n",
(float)(speed / 1000.), (float)(cPtr->MaxClock / 1000.));
cPtr->MaxClock = speed;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Max pixel clock is %7.3f MHz\n",
(float)(cPtr->MaxClock / 1000.));
}
real = 0.;
switch(bytesPerPixel) {
case 1:
if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_8, OPTUNITS_MHZ, &real))
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"FP clock %7.3f MHz requested\n",real);
break;
case 2:
if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_16, OPTUNITS_MHZ, &real))
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"FP clock %7.3f MHz requested\n",real);
break;
case 3:
if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_24, OPTUNITS_MHZ, &real))
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"FP clock %7.3f MHz requested\n",real);
break;
case 4:
if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_32, OPTUNITS_MHZ, &real))
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"FP clock %7.3f MHz requested\n",real);
break;
}
val = (int) (real * 1000.);
if (val && val >= cPtr->MinClock && val <= cPtr->MaxClock)
cPtr->FPclock = val;
else if (cPtr->FPclock > cPtr->MaxClock)
cPtr->FPclock = (int)((float)cPtr->MaxClock * 0.9);
else
cPtr->FPclock = 0;
cPtr->FPClkModified = FALSE;
if (cPtr->FPclock)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"FP clock set to %7.3f MHz\n",
(float)(cPtr->FPclock / 1000.));
#if defined(__arm32__) && defined(__NetBSD__)
ChipsPALMode.next = pScrn->monitor->Modes;
pScrn->monitor->Modes = &ChipsNTSCMode;
#endif
if (cPtr->Flags & ChipsDualChannelSupport) {
if (xf86IsEntityShared(pScrn->entityList[0])) {
if (cPtr->SecondCrtc == TRUE) {
cPtrEnt->slaveActive = FALSE;
} else {
cPtrEnt->masterActive = FALSE;
}
}
cPtr->writeIOSS(cPtr, cPtr->storeIOSS);
cPtr->writeMSS(cPtr, hwp, cPtr->storeMSS);
xf86SetPrimInitDone(pScrn->entityList[0]);
}
return TRUE;
}
static Bool
chipsPreInitWingine(ScrnInfoPtr pScrn, int flags)
{
int i, bytesPerPixel, NoClocks = 0;
unsigned char tmp;
MessageType from;
vgaHWPtr hwp;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
Bool useLinear = FALSE;
char *s;
resRange linearRes[] = { {ResExcMemBlock|ResBios|ResBus,0,0},_END };
pScrn->monitor = pScrn->confScreen->monitor;
if (cPtr->Flags & ChipsHDepthSupport)
i = xf86SetDepthBpp(pScrn, 0, 0, 0, Support24bppFb |
SupportConvert32to24 | PreferConvert32to24);
else
i = xf86SetDepthBpp(pScrn, 8, 0, 0, NoDepth24Support);
if (!i)
return FALSE;
else {
switch (pScrn->depth) {
case 1:
case 4:
case 8:
break;
case 15:
case 16:
case 24:
if (cPtr->Flags & ChipsHDepthSupport)
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Given depth (%d) is not supported by this driver\n",
pScrn->depth);
return FALSE;
}
}
xf86PrintDepthBpp(pScrn);
if (pScrn->depth == 24 && pix24bpp == 0)
pix24bpp = xf86GetBppFromDepth(pScrn, 24);
if (!vgaHWGetHWRec(pScrn))
return FALSE;
hwp = VGAHWPTR(pScrn);
vgaHWGetIOBase(hwp);
if (pScrn->depth > 8) {
rgb zeros = {0, 0, 0};
if (!xf86SetWeight(pScrn, zeros, zeros)) {
return FALSE;
} else {
;
}
}
if (!xf86SetDefaultVisual(pScrn, -1))
return FALSE;
if (pScrn->depth > 1) {
Gamma zeros = {0.0, 0.0, 0.0};
if (!xf86SetGamma(pScrn, zeros))
return FALSE;
}
cPtr->SuspendHack.xr02 = (cPtr->readXR(cPtr, 0x02)) & 0x18;
cPtr->SuspendHack.xr03 = (cPtr->readXR(cPtr, 0x03)) & 0x0A;
cPtr->SuspendHack.xr14 = (cPtr->readXR(cPtr, 0x14)) & 0x20;
cPtr->SuspendHack.xr15 = cPtr->readXR(cPtr, 0x15);
cPtr->SuspendHack.vgaIOBaseFlag = ((hwp->readMiscOut(hwp)) & 0x01);
cPtr->IOBase = (unsigned int)(cPtr->SuspendHack.vgaIOBaseFlag ?
0x3D0 : 0x3B0);
bytesPerPixel = max(1, pScrn->bitsPerPixel >> 3);
xf86CollectOptions(pScrn, NULL);
if (!(cPtr->Options = xalloc(sizeof(ChipsWingineOptions))))
return FALSE;
memcpy(cPtr->Options, ChipsWingineOptions, sizeof(ChipsWingineOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, cPtr->Options);
if (pScrn->depth > 1) {
pScrn->rgbBits = 6;
#if 0
if (xf86GetOptValInteger(cPtr->Options, OPTION_RGB_BITS,
&pScrn->rgbBits)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Bits per RGB set to %d\n",
pScrn->rgbBits);
}
#endif
}
if ((cPtr->Flags & ChipsAccelSupport) &&
(xf86ReturnOptValBool(cPtr->Options, OPTION_NOACCEL, FALSE))) {
cPtr->Flags &= ~ChipsAccelSupport;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Acceleration disabled\n");
}
from = X_DEFAULT;
if (pScrn->bitsPerPixel < 8) {
cPtr->Accel.UseHWCursor = FALSE;
} else {
cPtr->Accel.UseHWCursor = TRUE;
}
if (xf86GetOptValBool(cPtr->Options, OPTION_HW_CURSOR,
&cPtr->Accel.UseHWCursor))
from = X_CONFIG;
if (xf86GetOptValBool(cPtr->Options, OPTION_SW_CURSOR,
&cPtr->Accel.UseHWCursor)) {
from = X_CONFIG;
cPtr->Accel.UseHWCursor = !cPtr->Accel.UseHWCursor;
}
xf86DrvMsg(pScrn->scrnIndex, from, "Using %s cursor\n",
(cPtr->Accel.UseHWCursor) ? "HW" : "SW");
if (cPtr->pEnt->device->videoRam != 0) {
pScrn->videoRam = cPtr->pEnt->device->videoRam;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "VideoRAM: %d kByte\n",
pScrn->videoRam);
} else {
switch ((cPtr->readXR(cPtr, 0x0F)) & 3) {
case 0:
pScrn->videoRam = 256;
break;
case 1:
pScrn->videoRam = 512;
break;
case 2:
pScrn->videoRam = 1024;
break;
case 3:
pScrn->videoRam = 2048;
break;
}
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VideoRAM: %d kByte\n",
pScrn->videoRam);
}
cPtr->FbMapSize = pScrn->videoRam * 1024;
if (cPtr->Flags & ChipsLinearSupport) useLinear = TRUE;
if (pScrn->bitsPerPixel < 8) {
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE)) {
useLinear = FALSE;
from = X_CONFIG;
}
} else if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, TRUE)) {
useLinear = FALSE;
from = X_CONFIG;
}
if (useLinear) {
unsigned char mask = 0xF8;
if (pScrn->videoRam == 1024)
mask = 0xF0;
else if (pScrn->videoRam == 2048)
mask = 0xE0;
if (cPtr->pEnt->device->MemBase) {
cPtr->FbAddress = cPtr->pEnt->device->MemBase
& ((0xFF << 24) | (mask << 16));
from = X_CONFIG;
} else {
cPtr->FbAddress = ((0xFF & (cPtr->readXR(cPtr, 0x09))) << 24);
cPtr->FbAddress |= ((mask & (cPtr->readXR(cPtr, 0x08))) << 16);
from = X_PROBED;
}
linearRes[0].rBegin = cPtr->FbAddress;
linearRes[0].rEnd = cPtr->FbAddress + 0x800000;
if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
useLinear = FALSE;
from = X_PROBED;
}
}
if (useLinear) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Enabling linear addressing\n");
xf86DrvMsg(pScrn->scrnIndex, from,
"base address is set at 0x%lX.\n", cPtr->FbAddress);
if (xf86ReturnOptValBool(cPtr->Options, OPTION_MMIO, FALSE) &&
(cPtr->Flags & ChipsMMIOSupport)) {
cPtr->UseMMIO = TRUE;
cPtr->IOAddress = cPtr->FbAddress + 0x200000L;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling MMIO\n");
}
} else {
if (cPtr->Flags & ChipsLinearSupport)
xf86DrvMsg(pScrn->scrnIndex, from,
"Disabling linear addressing\n");
cPtr->Flags &= ~ChipsLinearSupport;
}
if ((s = xf86GetOptValString(cPtr->Options, OPTION_ROTATE))
|| xf86ReturnOptValBool(cPtr->Options, OPTION_SHADOW_FB, FALSE)) {
if (!(cPtr->Flags & ChipsLinearSupport)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Option \"ShadowFB\" ignored. Not supported without linear addressing\n");
} else if (pScrn->depth < 8) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Option \"ShadowFB\" ignored. Not supported at this depth.\n");
} else {
cPtr->Rotate = 0;
if (s) {
if(!xf86NameCmp(s, "CW")) {
cPtr->Flags |= ChipsShadowFB;
cPtr->Rotate = 1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Rotating screen clockwise\n");
} else if(!xf86NameCmp(s, "CCW")) {
cPtr->Flags |= ChipsShadowFB;
cPtr->Rotate = -1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rotating screen"
"counter clockwise\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "\"%s\" is not a valid"
"value for Option \"Rotate\"\n", s);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Valid options are \"CW\" or \"CCW\"\n");
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using \"Shadow Framebuffer\"\n");
cPtr->Flags |= ChipsShadowFB;
}
}
}
if (cPtr->Flags & ChipsShadowFB) {
if (cPtr->Flags & ChipsAccelSupport) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"HW acceleration is not supported with shadow fb\n");
cPtr->Flags &= ~ChipsAccelSupport;
}
if (cPtr->Rotate && cPtr->Accel.UseHWCursor) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"HW cursor is not supported with rotate\n");
cPtr->Accel.UseHWCursor = FALSE;
}
}
cPtr->PanelType |= ChipsCRT;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "CRT\n");
cPtr->Monitor = chipsSetMonitor(pScrn);
tmp = cPtr->readXR(cPtr, 0x01) & 3;
switch (tmp) {
case 0:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "ISA Bus\n");
cPtr->Bus = ChipsISA;
break;
case 3:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VL Bus\n");
cPtr->Bus = ChipsVLB;
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Unknown Bus\n");
cPtr->Bus = ChipsUnknown;
break;
}
if (pScrn->bitsPerPixel < 8) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Disabling acceleration for %d bpp\n", pScrn->bitsPerPixel);
cPtr->Flags &= ~ChipsAccelSupport;
}
if ((cPtr->Flags & ChipsAccelSupport) ||
(cPtr->Accel.UseHWCursor)) {
cPtr->Regs32 = xnfalloc(sizeof(ChipsReg32));
tmp = cPtr->readXR(cPtr, 0x07);
for( i = 0; i < (sizeof(ChipsReg32) / sizeof(ChipsReg32[0])); i++) {
cPtr->Regs32[i] = ((ChipsReg32[i] & 0x7E03)) | ((tmp & 0x80)
<< 8)| ((tmp & 0x7F) << 2);
#ifdef DEBUG
ErrorF("DR[%X] = %X\n",i,cPtr->Regs32[i]);
#endif
}
linearRes[0].type = ResExcIoSparse | ResBios | ResBus;
linearRes[0].rBase = cPtr->Regs32[0];
linearRes[0].rMask = 0x83FC;
if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
if (cPtr->Flags & ChipsAccelSupport) {
cPtr->Flags &= ~ChipsAccelSupport;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Cannot allocate IO registers: "
"Disabling acceleration\n");
}
if (cPtr->Accel.UseHWCursor) {
cPtr->Accel.UseHWCursor = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Cannot allocate IO registers: "
"Disabling HWCursor\n");
}
}
}
cPtr->ClockMulFactor = ((pScrn->bitsPerPixel >= 8) ? bytesPerPixel : 1);
if (cPtr->ClockMulFactor != 1)
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Clocks scaled by %d\n", cPtr->ClockMulFactor);
switch (cPtr->Chipset) {
case CHIPS_CT64200:
NoClocks = 4;
cPtr->ClockType = WINGINE_1_STYLE | TYPE_HW;
break;
default:
if (!((cPtr->readXR(cPtr, 0x01)) & 0x10)) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Using external clock generator\n");
NoClocks = 4;
cPtr->ClockType = WINGINE_1_STYLE | TYPE_HW;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Using internal clock generator\n");
if (xf86ReturnOptValBool(cPtr->Options, OPTION_HW_CLKS, FALSE)) {
NoClocks = 3;
cPtr->ClockType = WINGINE_2_STYLE | TYPE_HW;
} else {
NoClocks = 26;
cPtr->ClockType = WINGINE_2_STYLE | TYPE_PROGRAMMABLE;
pScrn->progClock = TRUE;
}
}
}
if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
pScrn->numClocks = NoClocks;
if(cPtr->pEnt->device->textClockFreq > 0) {
SaveClk->Clock = cPtr->pEnt->device->textClockFreq;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using textclock freq: %7.3f.\n",
SaveClk->Clock/1000.0);
} else
SaveClk->Clock = CRT_TEXT_CLK_FREQ;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Using programmable clocks\n");
} else {
SaveClk->Clock = chipsGetHWClock(pScrn);
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using textclock clock %i.\n",
SaveClk->Clock);
if (!cPtr->pEnt->device->numclocks) {
pScrn->numClocks = NoClocks;
xf86GetClocks(pScrn, NoClocks, chipsClockSelect,
chipsProtect, chipsBlankScreen,
cPtr->IOBase + 0x0A, 0x08, 1, 28322);
from = X_PROBED;
} else {
pScrn->numClocks = cPtr->pEnt->device->numclocks;
if (pScrn->numClocks > NoClocks) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Too many Clocks specified in configuration file.\n");
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"\t\tAt most %d clocks may be specified\n", NoClocks);
pScrn->numClocks= NoClocks;
}
for (i = 0; i < pScrn->numClocks; i++)
pScrn->clock[i] = cPtr->pEnt->device->clock[i];
from = X_CONFIG;
}
xf86ShowClocks(pScrn, from);
}
cPtr->MinClock = 11000 / cPtr->ClockMulFactor;
xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %7.3f MHz\n",
(float)(cPtr->MinClock / 1000.));
switch (cPtr->Chipset) {
case CHIPS_CT64200:
cPtr->MaxClock = 80000 / cPtr->ClockMulFactor;
break;
case CHIPS_CT64300:
cPtr->MaxClock = 85000 / cPtr->ClockMulFactor;
break;
}
if (cPtr->pEnt->device->dacSpeeds[0]) {
int speed = 0;
switch (pScrn->bitsPerPixel) {
case 1:
case 4:
case 8:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP8];
break;
case 16:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP16];
break;
case 24:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP24];
break;
}
if (speed == 0)
cPtr->MaxClock = cPtr->pEnt->device->dacSpeeds[0];
from = X_CONFIG;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"User max pixel clock of %7.3f MHz overrides %7.3f MHz limit\n",
(float)(cPtr->MaxClock / 1000.), (float)(speed / 1000.));
cPtr->MaxClock = speed;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Max pixel clock is %7.3f MHz\n",
(float)(cPtr->MaxClock / 1000.));
}
if (xf86LoadSubModule(pScrn, "ddc")) {
xf86LoaderReqSymLists(ddcSymbols, NULL);
if (cPtr->pVbe)
xf86SetDDCproperties(pScrn,xf86PrintEDID(vbeDoEDID(cPtr->pVbe, NULL)));
}
return TRUE;
}
static Bool
chipsPreInit655xx(ScrnInfoPtr pScrn, int flags)
{
int i, bytesPerPixel, NoClocks = 0;
unsigned char tmp;
MessageType from;
vgaHWPtr hwp;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSPanelSizePtr Size = &cPtr->PanelSize;
CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
Bool useLinear = FALSE;
char *s;
resRange linearRes[] = { {ResExcMemBlock|ResBios|ResBus,0,0},_END };
pScrn->monitor = pScrn->confScreen->monitor;
if (cPtr->Flags & ChipsHDepthSupport)
i = xf86SetDepthBpp(pScrn, 0, 0, 0, Support24bppFb |
SupportConvert32to24 | PreferConvert32to24);
else
i = xf86SetDepthBpp(pScrn, 8, 0, 0, NoDepth24Support);
if (!i)
return FALSE;
else {
switch (pScrn->depth) {
case 1:
case 4:
case 8:
break;
case 15:
case 16:
case 24:
if (cPtr->Flags & ChipsHDepthSupport)
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Given depth (%d) is not supported by this driver\n",
pScrn->depth);
return FALSE;
}
}
xf86PrintDepthBpp(pScrn);
if (pScrn->depth == 24 && pix24bpp == 0)
pix24bpp = xf86GetBppFromDepth(pScrn, 24);
if (!vgaHWGetHWRec(pScrn))
return FALSE;
hwp = VGAHWPTR(pScrn);
vgaHWGetIOBase(hwp);
if (pScrn->depth > 8) {
rgb zeros = {0, 0, 0};
if (!xf86SetWeight(pScrn, zeros, zeros)) {
return FALSE;
} else {
;
}
}
if (!xf86SetDefaultVisual(pScrn, -1))
return FALSE;
if (pScrn->depth > 1) {
Gamma zeros = {0.0, 0.0, 0.0};
if (!xf86SetGamma(pScrn, zeros))
return FALSE;
}
cPtr->SuspendHack.xr02 = (cPtr->readXR(cPtr, 0x02)) & 0x18;
cPtr->SuspendHack.xr03 = (cPtr->readXR(cPtr, 0x03)) & 0x0A;
cPtr->SuspendHack.xr14 = (cPtr->readXR(cPtr, 0x14)) & 0x20;
cPtr->SuspendHack.xr15 = cPtr->readXR(cPtr, 0x15);
cPtr->SuspendHack.vgaIOBaseFlag = ((hwp->readMiscOut(hwp)) & 0x01);
cPtr->IOBase = cPtr->SuspendHack.vgaIOBaseFlag ? 0x3D0 : 0x3B0;
bytesPerPixel = max(1, pScrn->bitsPerPixel >> 3);
xf86CollectOptions(pScrn, NULL);
if (!(cPtr->Options = xalloc(sizeof(Chips655xxOptions))))
return FALSE;
memcpy(cPtr->Options, Chips655xxOptions, sizeof(Chips655xxOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, cPtr->Options);
if (pScrn->depth > 1) {
pScrn->rgbBits = 6;
#if 0
if (xf86GetOptValInteger(cPtr->Options, OPTION_RGB_BITS,
&pScrn->rgbBits)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Bits per RGB set to %d\n",
pScrn->rgbBits);
}
#endif
}
if ((cPtr->Flags & ChipsAccelSupport) &&
(xf86ReturnOptValBool(cPtr->Options, OPTION_NOACCEL, FALSE))) {
cPtr->Flags &= ~ChipsAccelSupport;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Acceleration disabled\n");
}
from = X_DEFAULT;
if (pScrn->bitsPerPixel < 8) {
cPtr->Accel.UseHWCursor = FALSE;
} else {
cPtr->Accel.UseHWCursor = TRUE;
}
if (xf86GetOptValBool(cPtr->Options, OPTION_HW_CURSOR,
&cPtr->Accel.UseHWCursor))
from = X_CONFIG;
if (xf86GetOptValBool(cPtr->Options, OPTION_SW_CURSOR,
&cPtr->Accel.UseHWCursor)) {
from = X_CONFIG;
cPtr->Accel.UseHWCursor = !cPtr->Accel.UseHWCursor;
}
xf86DrvMsg(pScrn->scrnIndex, from, "Using %s cursor\n",
(cPtr->Accel.UseHWCursor) ? "HW" : "SW");
if (cPtr->pEnt->device->videoRam != 0) {
pScrn->videoRam = cPtr->pEnt->device->videoRam;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "VideoRAM: %d kByte\n",
pScrn->videoRam);
} else {
switch ((cPtr->readXR(cPtr, 0x0F)) & 3) {
case 0:
pScrn->videoRam = 256;
break;
case 1:
pScrn->videoRam = 512;
break;
case 2:
case 3:
pScrn->videoRam = 1024;
break;
}
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VideoRAM: %d kByte\n",
pScrn->videoRam);
}
cPtr->FbMapSize = pScrn->videoRam * 1024;
if (cPtr->Flags & ChipsLinearSupport) useLinear = TRUE;
if (pScrn->bitsPerPixel < 8) {
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE)) {
useLinear = FALSE;
from = X_CONFIG;
}
} else if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, TRUE)) {
useLinear = FALSE;
from = X_CONFIG;
}
if (useLinear) {
unsigned char mask;
if (cPtr->Chipset == CHIPS_CT65535) {
mask = (pScrn->videoRam > 512) ? 0xF8 :0xFC;
if (cPtr->Bus == ChipsISA)
mask &= 0x7F;
} else if (cPtr->Bus == ChipsISA) {
mask = 0x0F;
} else {
mask = 0xFF;
tmp = cPtr->readXR(cPtr, 0x01);
if(tmp & 0x40)
mask &= 0x3F;
if(!(tmp & 0x80))
mask &= 0xCF;
}
if (cPtr->pEnt->location.type == BUS_PCI) {
cPtr->FbAddress = cPtr->PciInfo->memBase[0] & 0xff800000;
if (xf86RegisterResources(cPtr->pEnt->index,NULL,ResNone))
useLinear = FALSE;
from = X_PROBED;
} else {
if (cPtr->pEnt->device->MemBase) {
cPtr->FbAddress = cPtr->pEnt->device->MemBase;
if (cPtr->Chipset == CHIPS_CT65535)
cPtr->FbAddress &= (mask << 17);
else if (cPtr->Chipset > CHIPS_CT65535)
cPtr->FbAddress &= (mask << 20);
from = X_CONFIG;
} else {
if (cPtr->Chipset <= CHIPS_CT65530) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"base address assumed at 0xC00000!\n");
cPtr->FbAddress = 0xC00000;
from = X_CONFIG;
} else if (cPtr->Chipset == CHIPS_CT65535) {
cPtr->FbAddress =
((mask & (cPtr->readXR(cPtr, 0x08))) << 17);
} else {
cPtr->FbAddress =
((mask & (cPtr->readXR(cPtr, 0x08))) << 20);
}
from = X_PROBED;
}
linearRes[0].rBegin = cPtr->FbAddress;
linearRes[0].rEnd = cPtr->FbAddress + 0x800000;
if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
useLinear = FALSE;
from = X_PROBED;
}
}
}
if (useLinear) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Enabling linear addressing\n");
xf86DrvMsg(pScrn->scrnIndex, from,
"base address is set at 0x%lX.\n", cPtr->FbAddress);
if (xf86ReturnOptValBool(cPtr->Options, OPTION_MMIO, FALSE) &&
(cPtr->Flags & ChipsMMIOSupport)) {
cPtr->UseMMIO = TRUE;
cPtr->IOAddress = cPtr->FbAddress + 0x200000L;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling MMIO\n");
}
} else {
if (cPtr->Flags & ChipsLinearSupport)
xf86DrvMsg(pScrn->scrnIndex, from,
"Disabling linear addressing\n");
cPtr->Flags &= ~ChipsLinearSupport;
}
if ((s = xf86GetOptValString(cPtr->Options, OPTION_ROTATE))
|| xf86ReturnOptValBool(cPtr->Options, OPTION_SHADOW_FB, FALSE)) {
if (!(cPtr->Flags & ChipsLinearSupport)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Option \"ShadowFB\" ignored. Not supported without linear addressing\n");
} else if (pScrn->depth < 8) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Option \"ShadowFB\" ignored. Not supported at this depth.\n");
} else {
cPtr->Rotate = 0;
if (s) {
if(!xf86NameCmp(s, "CW")) {
cPtr->Flags |= ChipsShadowFB;
cPtr->Rotate = 1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Rotating screen clockwise\n");
} else if(!xf86NameCmp(s, "CCW")) {
cPtr->Flags |= ChipsShadowFB;
cPtr->Rotate = -1;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rotating screen"
"counter clockwise\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "\"%s\" is not a valid"
"value for Option \"Rotate\"\n", s);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Valid options are \"CW\" or \"CCW\"\n");
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using \"Shadow Framebuffer\"\n");
cPtr->Flags |= ChipsShadowFB;
}
}
}
if (cPtr->Flags & ChipsShadowFB) {
if (cPtr->Flags & ChipsAccelSupport) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"HW acceleration is not supported with shadow fb\n");
cPtr->Flags &= ~ChipsAccelSupport;
}
if (cPtr->Rotate && cPtr->Accel.UseHWCursor) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"HW cursor is not supported with rotate\n");
cPtr->Accel.UseHWCursor = FALSE;
}
}
tmp = cPtr->readXR(cPtr, 0x51);
switch (tmp & 0x3) {
case 0:
if (xf86ReturnOptValBool(cPtr->Options, OPTION_STN, FALSE)) {
cPtr->PanelType |= ChipsSS;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "SS-STN probed\n");
} else {
cPtr->PanelType |= ChipsTFT;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "TFT probed\n");
}
break;
case 2:
cPtr->PanelType |= ChipsDS;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DS-STN probed\n");
case 3:
cPtr->PanelType |= ChipsDD;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DD-STN probed\n");
break;
default:
break;
}
chipsSetPanelType(cPtr);
from = X_PROBED;
{
Bool fp_mode;
if (xf86GetOptValBool(cPtr->Options, OPTION_FP_MODE, &fp_mode)) {
if (fp_mode) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing FP Mode on\n");
cPtr->PanelType |= ChipsLCD;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing FP Mode off\n");
cPtr->PanelType = ~ChipsLCD;
}
from = X_CONFIG;
}
}
if ((cPtr->PanelType & ChipsLCD) && (cPtr->PanelType & ChipsCRT))
xf86DrvMsg(pScrn->scrnIndex, from, "LCD/CRT\n");
else if (cPtr->PanelType & ChipsLCD)
xf86DrvMsg(pScrn->scrnIndex, from, "LCD\n");
else if (cPtr->PanelType & ChipsCRT) {
xf86DrvMsg(pScrn->scrnIndex, from, "CRT\n");
cPtr->Monitor = chipsSetMonitor(pScrn);
}
if (cPtr->PanelType & ChipsLCD) {
unsigned char xr17, tmp1;
char tmp2;
xr17 = cPtr->readXR(cPtr, 0x17);
tmp = cPtr->readXR(cPtr, 0x1B);
Size->HTotal =((tmp + ((xr17 & 0x01) << 8)) + 5) << 3;
tmp = cPtr->readXR(cPtr, 0x1C);
Size->HDisplay = ((tmp + ((xr17 & 0x02) << 7)) + 1) << 3;
tmp = cPtr->readXR(cPtr, 0x19);
Size->HRetraceStart = ((tmp + ((xr17 & 0x04) << 9)) + 1) << 3;
tmp1 = cPtr->readXR(cPtr, 0x1A);
tmp2 = (tmp1 & 0x1F) + ((xr17 & 0x08) << 2) - (tmp & 0x3F);
Size->HRetraceEnd = ((((tmp2 & 0x080u) ? (tmp2 + 0x40) : tmp2) << 3)
+ Size->HRetraceStart);
tmp1 = cPtr->readXR(cPtr, 0x65);
tmp = cPtr->readXR(cPtr, 0x68);
Size->VDisplay = ((tmp1 & 0x02) << 7)
+ ((tmp1 & 0x40) << 3) + tmp + 1;
tmp = cPtr->readXR(cPtr, 0x66);
Size->VRetraceStart = ((tmp1 & 0x04) << 6)
+ ((tmp1 & 0x80) << 2) + tmp + 1;
tmp = cPtr->readXR(cPtr, 0x64);
Size->VTotal = ((tmp1 & 0x01) << 8)
+ ((tmp1 & 0x20) << 4) + tmp + 2;
#ifdef DEBUG
ErrorF("x=%i, y=%i; xSync=%i, xSyncEnd=%i, xTotal=%i\n",
Size->HDisplay, Size->VDisplay,
Size->HRetraceStart, Size->HRetraceEnd,
Size->HTotal);
#endif
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Display Size: x=%i; y=%i\n",
Size->HDisplay, Size->VDisplay);
if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Display size overridden by modelines.\n");
}
}
if (IS_STN(cPtr->PanelType)) {
tmp = cPtr->readXR(cPtr, 0x6F);
if (tmp & 1) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Frame Buffer used\n");
if ((cPtr->Chipset > CHIPS_CT65530) && !(tmp & 0x80)) {
cPtr->FrameBufferSize = ( Size->HDisplay *
Size->VDisplay / 5 ) * ((tmp & 2) ? 1 : 2);
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Using embedded Frame Buffer, size %d bytes\n",
cPtr->FrameBufferSize);
} else
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Using external Frame Buffer used\n");
}
if (tmp & 2)
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Frame accelerator enabled\n");
}
if (cPtr->Chipset > CHIPS_CT65535) {
tmp = (cPtr->readXR(cPtr, 0x01)) & 7;
if (tmp == 6) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "PCI Bus\n");
cPtr->Bus = ChipsPCI;
if ((cPtr->Chipset == CHIPS_CT65545) ||
(cPtr->Chipset == CHIPS_CT65546)) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"32Bit IO not supported on 65545 PCI\n");
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "\tenabling MMIO\n");
cPtr->UseMMIO = TRUE;
cPtr->IOAddress = cPtr->FbAddress + 0x200000L;
}
} else {
switch (tmp) {
case 3:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "CPU Direct\n");
cPtr->Bus = ChipsCPUDirect;
break;
case 5:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "ISA Bus\n");
cPtr->Bus = ChipsISA;
break;
case 7:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VL Bus\n");
cPtr->Bus = ChipsVLB;
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Unknown Bus\n");
}
}
} else {
tmp = (cPtr->readXR(cPtr, 0x01)) & 3;
switch (tmp) {
case 0:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "PI Bus\n");
cPtr->Bus = ChipsPIB;
break;
case 1:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "MC Bus\n");
cPtr->Bus = ChipsMCB;
break;
case 2:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "VL Bus\n");
cPtr->Bus = ChipsVLB;
break;
case 3:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "ISA Bus\n");
cPtr->Bus = ChipsISA;
break;
}
}
if (!(cPtr->Bus == ChipsPCI) && (cPtr->UseMMIO)) {
cPtr->UseMMIO = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"MMIO only supported on PCI Bus. Disabling MMIO\n");
}
if (pScrn->bitsPerPixel < 8) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Disabling acceleration for %d bpp\n", pScrn->bitsPerPixel);
cPtr->Flags &= ~ChipsAccelSupport;
}
if ((cPtr->Chipset == CHIPS_CT65530) &&
(cPtr->Flags & ChipsLinearSupport)) {
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE))
cPtr->Flags &= ~ChipsLinearSupport;
if ((cPtr->Bus == ChipsISA) && (pScrn->videoRam > 512)) {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"User selected linear fb not supported by HW!\n");
cPtr->Flags &= ~ChipsLinearSupport;
}
}
if ((cPtr->readXR(cPtr, 0x06)) & 0x02)
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Internal DAC disabled\n");
if (cPtr->UseMMIO)
cPtr->Regs32 = ChipsReg32;
else if ((cPtr->Flags & ChipsAccelSupport) ||
(cPtr->Accel.UseHWCursor)) {
cPtr->Regs32 = xnfalloc(sizeof(ChipsReg32));
tmp = cPtr->readXR(cPtr, 0x07);
for (i = 0; i < (sizeof(ChipsReg32)/sizeof(ChipsReg32[0])); i++) {
cPtr->Regs32[i] =
((ChipsReg32[i] & 0x7E03)) | ((tmp & 0x80)<< 8)
| ((tmp & 0x7F) << 2);
#ifdef DEBUG
ErrorF("DR[%X] = %X\n",i,cPtr->Regs32[i]);
#endif
}
linearRes[0].type = ResExcIoSparse | ResBios | ResBus;
linearRes[0].rBase = cPtr->Regs32[0];
linearRes[0].rMask = 0x83FC;
if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
if (cPtr->Flags & ChipsAccelSupport) {
cPtr->Flags &= ~ChipsAccelSupport;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Cannot allocate IO registers: "
"Disabling acceleration\n");
}
if (cPtr->Accel.UseHWCursor) {
cPtr->Accel.UseHWCursor = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Cannot allocate IO registers: "
"Disabling HWCursor\n");
}
}
}
if (cPtr->Chipset > CHIPS_CT65530) {
tmp = cPtr->readXR(cPtr, 0x0E);
if (tmp & 0x80)
cPtr->SyncResetIgn = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Synchronous reset %signored.\n",
(cPtr->SyncResetIgn ? "" : "not "));
}
cPtr->ClockMulFactor = ((pScrn->bitsPerPixel >= 8) ? bytesPerPixel : 1);
if (cPtr->ClockMulFactor != 1)
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Clocks scaled by %d\n", cPtr->ClockMulFactor);
switch (cPtr->Chipset) {
case CHIPS_CT65520:
case CHIPS_CT65525:
case CHIPS_CT65530:
NoClocks = 4;
cPtr->ClockType = OLD_STYLE | TYPE_HW;
break;
default:
if (xf86ReturnOptValBool(cPtr->Options, OPTION_HW_CLKS, FALSE)) {
NoClocks = 5;
cPtr->ClockType = NEW_STYLE | TYPE_HW;
} else {
NoClocks = 26;
cPtr->ClockType = NEW_STYLE | TYPE_PROGRAMMABLE;
pScrn->progClock = TRUE;
}
}
if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
pScrn->numClocks = NoClocks;
if (cPtr->pEnt->device->textClockFreq > 0) {
SaveClk->Clock = cPtr->pEnt->device->textClockFreq;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using textclock freq: %7.3f.\n",
SaveClk->Clock/1000.0);
} else
SaveClk->Clock = ((cPtr->PanelType & ChipsLCDProbed) ?
LCD_TEXT_CLK_FREQ : CRT_TEXT_CLK_FREQ);
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Using programmable clocks\n");
} else {
SaveClk->Clock = chipsGetHWClock(pScrn);
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using textclock clock %i.\n",
SaveClk->Clock);
if (!cPtr->pEnt->device->numclocks) {
pScrn->numClocks = NoClocks;
xf86GetClocks(pScrn, NoClocks, chipsClockSelect,
chipsProtect, chipsBlankScreen,
cPtr->IOBase + 0x0A, 0x08, 1, 28322);
from = X_PROBED;
} else {
pScrn->numClocks = cPtr->pEnt->device->numclocks;
if (pScrn->numClocks > NoClocks) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Too many Clocks specified in configuration file.\n");
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"\t\tAt most %d clocks may be specified\n", NoClocks);
pScrn->numClocks = NoClocks;
}
for (i = 0; i < pScrn->numClocks; i++)
pScrn->clock[i] = cPtr->pEnt->device->clock[i];
from = X_CONFIG;
}
xf86ShowClocks(pScrn, from);
}
cPtr->MinClock = 11000 / cPtr->ClockMulFactor;
xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %7.3f MHz\n",
(float)(cPtr->MinClock / 1000.));
switch (cPtr->Chipset) {
case CHIPS_CT65546:
case CHIPS_CT65548:
cPtr->MaxClock = 80000 / cPtr->ClockMulFactor;
break;
default:
if ((cPtr->readXR(cPtr, 0x6C)) & 2) {
cPtr->MaxClock = 68000 / cPtr->ClockMulFactor;
} else {
cPtr->MaxClock = 56000 / cPtr->ClockMulFactor;
}
}
if (cPtr->pEnt->device->dacSpeeds[0]) {
int speed = 0;
switch (pScrn->bitsPerPixel) {
case 1:
case 4:
case 8:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP8];
break;
case 16:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP16];
break;
case 24:
speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP24];
break;
}
if (speed == 0)
cPtr->MaxClock = cPtr->pEnt->device->dacSpeeds[0];
from = X_CONFIG;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"User max pixel clock of %7.3f MHz overrides %7.3f MHz limit\n",
(float)(cPtr->MaxClock / 1000.), (float)(speed / 1000.));
cPtr->MaxClock = speed;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Max pixel clock is %7.3f MHz\n",
(float)(cPtr->MaxClock / 1000.));
}
if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
double real = 0;
switch(bytesPerPixel) {
case 1:
xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_8,
OPTUNITS_MHZ, &real);
break;
case 2:
xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_16,
OPTUNITS_MHZ, &real);
break;
case 3:
xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_24,
OPTUNITS_MHZ, &real);
break;
}
if (real > 0) {
int val;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"FP clock %7.3f MHz requested\n",real);
val = (int) (real * 1000.);
if (val && (val >= cPtr->MinClock)
&& (val <= cPtr->MaxClock))
cPtr->FPclock = val * cPtr->ClockMulFactor;
else if (val > cPtr->MaxClock)
cPtr->FPclock = (int)((float)cPtr->MaxClock
* cPtr->ClockMulFactor * 0.9);
else
cPtr->FPclock = 0;
} else
cPtr->FPclock = 0;
if (cPtr->FPclock)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"FP clock set to %7.3f MHz\n",
(float)(cPtr->FPclock / 1000.));
} else {
if (xf86IsOptionSet(cPtr->Options, OPTION_SET_MCLK))
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"FP clock option not supported for this chipset\n");
}
if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
double real;
switch (cPtr->Chipset) {
case CHIPS_CT65546:
case CHIPS_CT65548:
cPtr->MemClock.Max = 75000;
break;
default:
if ((cPtr->readXR(cPtr, 0x6C)) & 2) {
cPtr->MemClock.Max = 68000;
} else {
cPtr->MemClock.Max = 56000;
}
}
if (xf86GetOptValFreq(cPtr->Options, OPTION_SET_MCLK,
OPTUNITS_MHZ, &real)) {
int mclk = (int)(real * 1000.0);
if (mclk <= cPtr->MemClock.Max) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using memory clock of %7.3f MHz\n",
(float)(mclk/1000.));
cPtr->MemClock.Clk = mclk;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
"Memory clock of %7.3f MHz exceeds limit of "
"%7.3f MHz\n",(float)(mclk/1000.),
(float)(cPtr->MemClock.Max/1000.));
cPtr->MemClock.Clk = cPtr->MemClock.Max * 0.9;
}
} else
cPtr->MemClock.Clk = 0;
} else
if (xf86IsOptionSet(cPtr->Options, OPTION_SET_MCLK))
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Memory clock option not supported for this chipset\n");
if (xf86LoadSubModule(pScrn, "ddc")) {
xf86LoaderReqSymLists(ddcSymbols, NULL);
if (cPtr->pVbe)
xf86SetDDCproperties(pScrn,xf86PrintEDID(vbeDoEDID(cPtr->pVbe, NULL)));
}
return TRUE;
}
static Bool
CHIPSEnterVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSEntPtr cPtrEnt;
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALOPEN;
}
if(!chipsModeInit(pScrn, pScrn->currentMode))
return FALSE;
if ((!(cPtr->Flags & ChipsOverlay8plus16))
&& (cPtr->Flags & ChipsVideoSupport)
&& (cPtr->Flags & ChipsLinearSupport))
CHIPSResetVideo(pScrn);
chipsHWCursorOn(cPtr, pScrn);
xf86UDelay(50000);
CHIPSAdjustFrame(pScrn->scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
xf86UDelay(50000);
return TRUE;
}
static void
CHIPSLeaveVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSACLPtr cAcl = CHIPSACLPTR(pScrn);
CHIPSEntPtr cPtrEnt;
cAcl->planemask = -1;
cAcl->fgColor = -1;
cAcl->bgColor = -1;
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
if (cPtr->UseDualChannel)
DUALREOPEN;
DUALCLOSE;
} else {
chipsHWCursorOff(cPtr, pScrn);
chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,
TRUE);
chipsLock(pScrn);
}
}
static void
chipsLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
VisualPtr pVisual)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int i, index, shift ;
CHIPSEntPtr cPtrEnt;
shift = ((pScrn->depth == 15) &&
(!(cPtr->Flags & ChipsOverlay8plus16))) ? 3 : 0;
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
for (i = 0; i < numColors; i++) {
index = indices[i];
hwp->writeDacWriteAddr(hwp,index << shift);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].red);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].green);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].blue);
DACDelay(hwp);
}
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
for (i = 0; i < numColors; i++) {
index = indices[i];
hwp->writeDacWriteAddr(hwp,index << shift);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].red);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].green);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].blue);
DACDelay(hwp);
}
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
}
hwp->disablePalette(hwp);
}
static void
chipsLoadPalette16(ScrnInfoPtr pScrn, int numColors, int *indices,
LOCO *colors, VisualPtr pVisual)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSEntPtr cPtrEnt;
int i, index;
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
for (i = 0; i < numColors; i++) {
index = indices[i];
hwp->writeDacWriteAddr(hwp, index << 2);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index >> 1].red);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].green);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index >> 1].blue);
DACDelay(hwp);
}
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
for (i = 0; i < numColors; i++) {
index = indices[i];
hwp->writeDacWriteAddr(hwp, index << 2);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index >> 1].red);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index].green);
DACDelay(hwp);
hwp->writeDacData(hwp, colors[index >> 1].blue);
DACDelay(hwp);
}
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
}
hwp->disablePalette(hwp);
}
static Bool
CHIPSScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
vgaHWPtr hwp;
CHIPSPtr cPtr;
CHIPSACLPtr cAcl;
int ret;
int init_picture = 0;
VisualPtr visual;
int allocatebase, freespace, currentaddr;
unsigned int racflag = 0;
unsigned char *FBStart;
int height, width, displayWidth;
CHIPSEntPtr cPtrEnt = NULL;
#ifdef DEBUG
ErrorF("CHIPSScreenInit\n");
#endif
cPtr = CHIPSPTR(pScrn);
cAcl = CHIPSACLPTR(pScrn);
hwp = VGAHWPTR(pScrn);
hwp->MapSize = 0x10000;
if (!vgaHWMapMem(pScrn))
return FALSE;
if (!chipsMapMem(pScrn))
return FALSE;
if (cPtr->Flags & ChipsOverlay8plus16) {
cPtr->FbOffset16 = pScrn->displayWidth * pScrn->virtualY;
cPtr->FbSize16 = (pScrn->displayWidth << 1) * pScrn->virtualY;
if (cPtr->FbSize16 > (cPtr->FbMapSize - cPtr->FrameBufferSize)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Too little memory for overlay. Disabling.\n");
cPtr->Flags &= ~ChipsOverlay8plus16;
}
if ((pScrn->displayWidth > 1024) || (pScrn->virtualY > 1024)) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Max overlay Width/Height 1024 pixels. Disabling.\n");
cPtr->Flags &= ~ChipsOverlay8plus16;
}
}
if (cPtr->UseFullMMIO && cPtr->MMIOBaseVGA) {
CHIPSSetMmioExtFuncs(cPtr);
CHIPSHWSetMmioFuncs(pScrn, cPtr->MMIOBaseVGA, 0x0);
}
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALOPEN;
}
#if defined(__arm32__) && defined(__NetBSD__)
if (strcmp(pScrn->currentMode->name,"PAL") == 0) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using built-in PAL TV mode\n");
cPtr->TVMode = XMODE_PAL;
} else if (strcmp(pScrn->currentMode->name,"SECAM") == 0){
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using built-in SECAM TV mode\n");
cPtr->TVMode = XMODE_SECAM;
} else if (strcmp(pScrn->currentMode->name,"NTSC") == 0) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"Using built-in NTSC TV mode\n");
cPtr->TVMode = XMODE_NTSC;
} else
cPtr->TVMode = XMODE_RGB;
#endif
if ((cPtr->Flags & ChipsDualChannelSupport) &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_A));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_A));
chipsSave(pScrn, &hwp->SavedReg, &cPtr->SavedReg);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
chipsSave(pScrn, &cPtr->VgaSavedReg2, &cPtr->SavedReg2);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
} else
chipsSave(pScrn, &hwp->SavedReg, &cPtr->SavedReg);
if (!chipsModeInit(pScrn,pScrn->currentMode))
return FALSE;
CHIPSSaveScreen(pScreen,SCREEN_SAVER_ON);
CHIPSAdjustFrame(pScrn->scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
miClearVisualTypes();
if ((pScrn->bitsPerPixel == 16) && (cPtr->Flags & ChipsOverlay8plus16)){
if (!miSetVisualTypes(8, PseudoColorMask | GrayScaleMask,
pScrn->rgbBits, PseudoColor))
return FALSE;
if (!miSetVisualTypes(16, TrueColorMask, pScrn->rgbBits, TrueColor))
return FALSE;
} else {
if (!miSetVisualTypes(pScrn->depth,
miGetDefaultVisualMask(pScrn->depth),
pScrn->rgbBits, pScrn->defaultVisual))
return FALSE;
}
miSetPixmapDepths ();
if ((cPtr->Flags & ChipsShadowFB) && cPtr->Rotate) {
height = pScrn->virtualX;
width = pScrn->virtualY;
} else {
width = pScrn->virtualX;
height = pScrn->virtualY;
}
if(cPtr->Flags & ChipsShadowFB) {
cPtr->ShadowPitch = BitmapBytePad(pScrn->bitsPerPixel * width);
cPtr->ShadowPtr = xalloc(cPtr->ShadowPitch * height);
displayWidth = cPtr->ShadowPitch / (pScrn->bitsPerPixel >> 3);
FBStart = cPtr->ShadowPtr;
} else {
cPtr->ShadowPtr = NULL;
displayWidth = pScrn->displayWidth;
FBStart = cPtr->FbBase;
}
switch (pScrn->bitsPerPixel) {
case 1:
ret = xf1bppScreenInit(pScreen, FBStart,
width,height,
pScrn->xDpi, pScrn->yDpi,
displayWidth);
break;
case 4:
ret = xf4bppScreenInit(pScreen, FBStart,
width,height,
pScrn->xDpi, pScrn->yDpi,
displayWidth);
break;
case 16:
if (cPtr->Flags & ChipsOverlay8plus16) {
ret = cfb8_16ScreenInit(pScreen, (unsigned char *)FBStart +
cPtr->FbOffset16, FBStart, width,
height, pScrn->xDpi, pScrn->yDpi,
displayWidth, displayWidth);
break;
}
default:
ret = fbScreenInit(pScreen, FBStart,
width,height,
pScrn->xDpi, pScrn->yDpi,
displayWidth,pScrn->bitsPerPixel);
init_picture = 1;
break;
}
if (!ret)
return FALSE;
if (pScrn->depth > 8) {
visual = pScreen->visuals + pScreen->numVisuals;
while (--visual >= pScreen->visuals) {
if ((visual->class | DynamicClass) == DirectColor) {
visual->offsetRed = pScrn->offset.red;
visual->offsetGreen = pScrn->offset.green;
visual->offsetBlue = pScrn->offset.blue;
visual->redMask = pScrn->mask.red;
visual->greenMask = pScrn->mask.green;
visual->blueMask = pScrn->mask.blue;
}
}
}
if (init_picture)
fbPictureInit (pScreen, 0, 0);
xf86SetBlackWhitePixels(pScreen);
cPtr->BlockHandler = pScreen->BlockHandler;
pScreen->BlockHandler = chipsBlockHandler;
if ( (pScrn->depth >= 8))
CHIPSDGAInit(pScreen);
cPtr->HWCursorShown = FALSE;
if (!(cPtr->Flags & ChipsLinearSupport)) {
miBankInfoPtr pBankInfo;
pBankInfo = (miBankInfoPtr)xnfcalloc(sizeof(miBankInfoRec),1);
if (pBankInfo == NULL)
return FALSE;
#if defined(__arm32__)
cPtr->Bank = -1;
#endif
pBankInfo->pBankA = hwp->Base;
pBankInfo->pBankB = (unsigned char *)hwp->Base + 0x08000;
pBankInfo->BankSize = 0x08000;
pBankInfo->nBankDepth = (pScrn->depth == 4) ? 1 : pScrn->depth;
if (IS_HiQV(cPtr)) {
pBankInfo->pBankB = hwp->Base;
pBankInfo->BankSize = 0x10000;
if (pScrn->bitsPerPixel < 8) {
pBankInfo->SetSourceBank =
(miBankProcPtr)CHIPSHiQVSetReadWritePlanar;
pBankInfo->SetDestinationBank =
(miBankProcPtr)CHIPSHiQVSetReadWritePlanar;
pBankInfo->SetSourceAndDestinationBanks =
(miBankProcPtr)CHIPSHiQVSetReadWritePlanar;
} else {
pBankInfo->SetSourceBank =
(miBankProcPtr)CHIPSHiQVSetReadWrite;
pBankInfo->SetDestinationBank =
(miBankProcPtr)CHIPSHiQVSetReadWrite;
pBankInfo->SetSourceAndDestinationBanks =
(miBankProcPtr)CHIPSHiQVSetReadWrite;
}
} else {
if (IS_Wingine(cPtr)) {
if (pScrn->bitsPerPixel < 8) {
pBankInfo->SetSourceBank =
(miBankProcPtr)CHIPSWINSetReadPlanar;
pBankInfo->SetDestinationBank =
(miBankProcPtr)CHIPSWINSetWritePlanar;
pBankInfo->SetSourceAndDestinationBanks =
(miBankProcPtr)CHIPSWINSetReadWritePlanar;
} else {
pBankInfo->SetSourceBank = (miBankProcPtr)CHIPSWINSetRead;
pBankInfo->SetDestinationBank =
(miBankProcPtr)CHIPSWINSetWrite;
pBankInfo->SetSourceAndDestinationBanks =
(miBankProcPtr)CHIPSWINSetReadWrite;
}
} else {
if (pScrn->bitsPerPixel < 8) {
pBankInfo->SetSourceBank =
(miBankProcPtr)CHIPSSetReadPlanar;
pBankInfo->SetDestinationBank =
(miBankProcPtr)CHIPSSetWritePlanar;
pBankInfo->SetSourceAndDestinationBanks =
(miBankProcPtr)CHIPSSetReadWritePlanar;
} else {
pBankInfo->SetSourceBank = (miBankProcPtr)CHIPSSetRead;
pBankInfo->SetDestinationBank =
(miBankProcPtr)CHIPSSetWrite;
pBankInfo->SetSourceAndDestinationBanks =
(miBankProcPtr)CHIPSSetReadWrite;
}
}
}
if (!miInitializeBanking(pScreen, pScrn->virtualX, pScrn->virtualY,
pScrn->displayWidth, pBankInfo)) {
xfree(pBankInfo);
pBankInfo = NULL;
return FALSE;
}
miInitializeBackingStore(pScreen);
xf86SetBackingStore(pScreen);
miDCInitialize (pScreen, xf86GetPointerScreenFuncs());
} else {
#define CHIPSALIGN(size, align) (currentaddr - ((currentaddr - size) & ~align))
allocatebase = (pScrn->videoRam<<10) - cPtr->FrameBufferSize;
if (pScrn->bitsPerPixel < 8)
freespace = allocatebase - pScrn->displayWidth *
pScrn->virtualY / 2;
else if ((pScrn->bitsPerPixel == 16) && (cPtr->Flags & ChipsOverlay8plus16))
freespace = allocatebase - pScrn->displayWidth *
pScrn->virtualY - cPtr->FbSize16;
else
freespace = allocatebase - pScrn->displayWidth *
pScrn->virtualY * (pScrn->bitsPerPixel >> 3);
if ((cPtr->Flags & ChipsDualChannelSupport) &&
(cPtr->SecondCrtc == TRUE)) {
currentaddr = allocatebase + cPtrEnt->masterFbMapSize;
} else
currentaddr = allocatebase;
if (serverGeneration == 1)
xf86DrvMsg(scrnIndex, X_PROBED,
"%d bytes off-screen memory available\n", freespace);
if (cAcl->UseHWCursor) {
cAcl->CursorAddress = -1;
if (IS_HiQV(cPtr)) {
if (CHIPSALIGN(1024, 0xFFF) <= freespace) {
currentaddr -= CHIPSALIGN(1024, 0xFFF);
freespace -= CHIPSALIGN(1024, 0xFFF);
cAcl->CursorAddress = currentaddr;
}
} else if (IS_Wingine(cPtr)) {
cAcl->CursorAddress = 0;
} else if (CHIPSALIGN(1024, 0x3FF) <= freespace) {
currentaddr -= CHIPSALIGN(1024, 0x3FF);
freespace -= CHIPSALIGN(1024, 0x3FF);
cAcl->CursorAddress = currentaddr;
}
if (cAcl->CursorAddress == -1)
xf86DrvMsg(scrnIndex, X_ERROR,
"Too little space for H/W cursor.\n");
}
cAcl->CacheEnd = currentaddr;
if (cPtr->Flags & ChipsAccelSupport) {
cAcl->ScratchAddress = -1;
switch (pScrn->bitsPerPixel) {
case 8:
if (CHIPSALIGN(64, 0x3F) <= freespace) {
currentaddr -= CHIPSALIGN(64, 0x3F);
freespace -= CHIPSALIGN(64, 0x3F);
cAcl->ScratchAddress = currentaddr;
}
break;
case 16:
if (CHIPSALIGN(128, 0x7F) <= freespace) {
currentaddr -= CHIPSALIGN(128, 0x7F);
freespace -= CHIPSALIGN(128, 0x7F);
cAcl->ScratchAddress = currentaddr;
}
break;
case 24:
if (!IS_HiQV(cPtr)) {
if (CHIPSALIGN(3 * (pScrn->displayWidth + 4), 0x3)
<= freespace) {
currentaddr -= CHIPSALIGN(3 * (pScrn->displayWidth
+ 4), 0x3);
freespace -= CHIPSALIGN(3 * (pScrn->displayWidth + 4),
0x3);
cAcl->ScratchAddress = currentaddr;
}
}
break;
case 32:
if (IS_HiQV(cPtr)) {
if (CHIPSALIGN(8, 0x7) <= freespace) {
currentaddr -= CHIPSALIGN(8, 0x7);
freespace -= CHIPSALIGN(8, 0x7);
cAcl->ScratchAddress = currentaddr;
}
}
break;
}
cAcl->CacheStart = currentaddr - freespace;
cAcl->CacheEnd = currentaddr;
if (cAcl->CacheStart >= cAcl->CacheEnd) {
xf86DrvMsg(scrnIndex, X_ERROR,
"Too little space for pixmap cache.\n");
cAcl->CacheStart = 0;
cAcl->CacheEnd = 0;
}
if (IS_HiQV(cPtr))
cAcl->BltDataWindow = (unsigned char *)cPtr->MMIOBase
+ 0x10000L;
else
cAcl->BltDataWindow = cPtr->FbBase;
}
{
BoxRec AvailFBArea;
AvailFBArea.x1 = 0;
AvailFBArea.y1 = 0;
AvailFBArea.x2 = pScrn->displayWidth;
AvailFBArea.y2 = cAcl->CacheEnd /
(pScrn->displayWidth * (pScrn->bitsPerPixel >> 3));
if (!(cPtr->Flags & ChipsOverlay8plus16)) {
xf86InitFBManager(pScreen, &AvailFBArea);
}
}
if (cPtr->Flags & ChipsAccelSupport) {
if (IS_HiQV(cPtr)) {
CHIPSHiQVAccelInit(pScreen);
} else if (cPtr->UseMMIO) {
CHIPSMMIOAccelInit(pScreen);
} else {
CHIPSAccelInit(pScreen);
}
}
miInitializeBackingStore(pScreen);
xf86SetBackingStore(pScreen);
#ifdef ENABLE_SILKEN_MOUSE
xf86SetSilkenMouse(pScreen);
#endif
miDCInitialize (pScreen, xf86GetPointerScreenFuncs());
if ((cAcl->UseHWCursor) && (cAcl->CursorAddress != -1)) {
if (!CHIPSCursorInit(pScreen)) {
xf86DrvMsg(scrnIndex, X_ERROR,
"Hardware cursor initialization failed\n");
return FALSE;
}
}
}
if (cPtr->Flags & ChipsShadowFB) {
RefreshAreaFuncPtr refreshArea = chipsRefreshArea;
if(cPtr->Rotate) {
if (!cPtr->PointerMoved) {
cPtr->PointerMoved = pScrn->PointerMoved;
pScrn->PointerMoved = chipsPointerMoved;
}
switch(pScrn->bitsPerPixel) {
case 8: refreshArea = chipsRefreshArea8; break;
case 16: refreshArea = chipsRefreshArea16; break;
case 24: refreshArea = chipsRefreshArea24; break;
case 32: refreshArea = chipsRefreshArea32; break;
}
}
ShadowFBInit(pScreen, refreshArea);
}
if (!miCreateDefColormap(pScreen))
return FALSE;
if ((cPtr->Flags & ChipsOverlay8plus16) && (pScrn->bitsPerPixel == 16)) {
if(!xf86HandleColormaps(pScreen, 256, pScrn->rgbBits, chipsLoadPalette,
NULL, CMAP_RELOAD_ON_MODE_SWITCH))
return FALSE;
} else {
if(!xf86HandleColormaps(pScreen, 256, pScrn->rgbBits,
(pScrn->depth == 16 ? chipsLoadPalette16 : chipsLoadPalette),
NULL, CMAP_RELOAD_ON_MODE_SWITCH | CMAP_PALETTED_TRUECOLOR))
return FALSE;
}
racflag = RAC_COLORMAP;
if (cAcl->UseHWCursor)
racflag |= RAC_CURSOR;
racflag |= (RAC_FB | RAC_VIEWPORT);
pScrn->racIoFlags = pScrn->racMemFlags = racflag;
#ifdef ENABLE_SILKEN_MOUSE
xf86SetSilkenMouse(pScreen);
#endif
if ((!(cPtr->Flags & ChipsOverlay8plus16))
&& (cPtr->Flags & ChipsVideoSupport)
&& (cPtr->Flags & ChipsLinearSupport)) {
CHIPSInitVideo(pScreen);
}
pScreen->SaveScreen = CHIPSSaveScreen;
if (cPtr->Flags & ChipsDPMSSupport)
xf86DPMSInit(pScreen, (DPMSSetProcPtr)chipsDisplayPowerManagementSet,
0);
#if 0
if ((cPtr->Flags & ChipsDualChannelSupport) &&
(cPtr->SecondCrtc == TRUE))
pScrn->memPhysBase = cPtr->FbAddress + cPtrEnt->masterFbMapSize;
#endif
cPtr->CloseScreen = pScreen->CloseScreen;
pScreen->CloseScreen = CHIPSCloseScreen;
if (serverGeneration == 1) {
xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
}
return TRUE;
}
Bool
CHIPSSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSEntPtr cPtrEnt;
#ifdef DEBUG
ErrorF("CHIPSSwitchMode\n");
#endif
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
return chipsModeInit(xf86Screens[scrnIndex], mode);
}
void
CHIPSAdjustFrame(int scrnIndex, int x, int y, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSEntPtr cPtrEnt;
int Base;
vgaHWPtr hwp = VGAHWPTR(pScrn);
unsigned char tmp;
if (xf86ReturnOptValBool(cPtr->Options, OPTION_SHOWCACHE, FALSE) && y) {
int lastline = cPtr->FbMapSize /
((pScrn->displayWidth * pScrn->bitsPerPixel) / 8);
lastline -= pScrn->currentMode->VDisplay;
y += pScrn->virtualY - 1;
if (y > lastline) y = lastline;
}
Base = y * pScrn->displayWidth + x;
switch (pScrn->bitsPerPixel) {
case 1:
case 4:
Base >>= 3;
break;
case 16:
if (!(cPtr->Flags & ChipsOverlay8plus16))
Base >>= 1;
else
Base >>= 2;
break;
case 24:
if (!IS_HiQV(cPtr))
Base = (Base >> 2) * 3;
else
Base = (Base >> 3) * 6;
break;
case 32:
break;
default:
Base >>= 2;
break;
}
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
chipsFixResume(pScrn);
hwp->writeCrtc(hwp, 0x0C, (Base & 0xFF00) >> 8);
hwp->writeCrtc(hwp, 0x0D, Base & 0xFF);
if (IS_HiQV(cPtr)) {
if (((cPtr->readXR(cPtr, 0x09)) & 0x1) == 0x1)
hwp->writeCrtc(hwp, 0x40, ((Base & 0x0F0000) >> 16) | 0x80);
} else {
tmp = cPtr->readXR(cPtr, 0x0C);
cPtr->writeXR(cPtr, 0x0C, ((Base & (IS_Wingine(cPtr) ? 0x0F0000 :
0x030000)) >> 16) | (tmp & 0xF8));
}
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
chipsFixResume(pScrn);
hwp->writeCrtc(hwp, 0x0C, (Base & 0xFF00) >> 8);
hwp->writeCrtc(hwp, 0x0D, Base & 0xFF);
if (((cPtr->readXR(cPtr, 0x09)) & 0x1) == 0x1)
hwp->writeCrtc(hwp, 0x40, ((Base & 0x0F0000) >> 16) | 0x80);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
}
if (cPtr->Flags & ChipsOverlay8plus16) {
Base = (Base << 3) & ~(unsigned long)0xF;
cPtr->writeMR(cPtr, 0x22, (cPtr->FbOffset16 + Base) & 0xF8);
cPtr->writeMR(cPtr, 0x23, ((cPtr->FbOffset16 + Base) >> 8) & 0xFF);
cPtr->writeMR(cPtr, 0x24, ((cPtr->FbOffset16 + Base) >> 16) & 0xFF);
}
}
static Bool
CHIPSCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSEntPtr cPtrEnt;
if(pScrn->vtSema){
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
if (cPtr->UseDualChannel)
DUALREOPEN;
DUALCLOSE;
} else {
chipsHWCursorOff(cPtr, pScrn);
chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,
TRUE);
chipsLock(pScrn);
}
chipsUnmapMem(pScrn);
}
if (xf86IsEntityShared(pScrn->entityList[0])) {
DevUnion *pPriv;
pPriv = xf86GetEntityPrivate(pScrn->entityList[0], CHIPSEntityIndex);
cPtrEnt = pPriv->ptr;
cPtrEnt->refCount--;
}
if (cPtr->AccelInfoRec)
XAADestroyInfoRec(cPtr->AccelInfoRec);
if (cPtr->CursorInfoRec)
xf86DestroyCursorInfoRec(cPtr->CursorInfoRec);
if (cPtr->ShadowPtr)
xfree(cPtr->ShadowPtr);
if (cPtr->DGAModes)
xfree(cPtr->DGAModes);
pScrn->vtSema = FALSE;
if(cPtr->BlockHandler)
pScreen->BlockHandler = cPtr->BlockHandler;
pScreen->CloseScreen = cPtr->CloseScreen;
xf86ClearPrimInitDone(pScrn->entityList[0]);
return (*pScreen->CloseScreen)(scrnIndex, pScreen);
}
static void
CHIPSFreeScreen(int scrnIndex, int flags)
{
if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
vgaHWFreeHWRec(xf86Screens[scrnIndex]);
CHIPSFreeRec(xf86Screens[scrnIndex]);
}
static ModeStatus
CHIPSValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
if (flags & MODECHECK_FINAL) {
if ((cPtr->Flags & ChipsOverlay8plus16)
&& ((pScrn->videoRam<<10) - pScrn->displayWidth * 3 * pScrn->virtualY
< 0))
return MODE_MEM;
}
if ((mode->Flags & V_INTERLACE) && (cPtr->PanelType & ChipsLCD))
return MODE_NO_INTERLACE;
if ((cPtr->PanelType & ChipsLCD)
&& !xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)
&& ((cPtr->PanelSize.HDisplay < mode->HDisplay)
|| (cPtr->PanelSize.VDisplay < mode->VDisplay)))
return MODE_PANEL;
return MODE_OK;
}
static void
chipsDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
int flags)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSEntPtr cPtrEnt;
unsigned char dpmsreg, seqreg, lcdoff, tmp;
if (!pScrn->vtSema)
return;
xf86EnableAccess(pScrn);
switch (PowerManagementMode) {
case DPMSModeOn:
dpmsreg = 0x00;
seqreg = 0x00;
lcdoff = 0x0;
break;
case DPMSModeStandby:
dpmsreg = 0x02;
seqreg = 0x20;
lcdoff = 0x0;
break;
case DPMSModeSuspend:
dpmsreg = 0x08;
seqreg = 0x20;
lcdoff = 0x1;
break;
case DPMSModeOff:
dpmsreg = 0x0A;
seqreg = 0x20;
lcdoff = 0x1;
break;
default:
return;
}
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
seqreg |= hwp->readSeq(hwp, 0x01) & ~0x20;
hwp->writeSeq(hwp, 0x01, seqreg);
if (IS_HiQV(cPtr)) {
tmp = cPtr->readXR(cPtr, 0x61);
cPtr->writeXR(cPtr, 0x61, (tmp & 0xF0) | dpmsreg);
} else {
tmp = cPtr->readXR(cPtr, 0x73);
cPtr->writeXR(cPtr, 0x73, (tmp & 0xF0) | dpmsreg);
}
if (cPtr->PanelType & ChipsLCDProbed) {
if (IS_HiQV(cPtr)) {
if (cPtr->Chipset == CHIPS_CT69030) {
#if 0
tmp = cPtr->readFR(cPtr, 0x05);
if (lcdoff)
cPtr->writeFR(cPtr, 0x05, tmp | 0x08);
else
cPtr->writeFR(cPtr, 0x05, tmp & 0xF7);
#endif
} else {
tmp = cPtr->readFR(cPtr, 0x05);
if (lcdoff)
cPtr->writeFR(cPtr, 0x05, tmp | 0x08);
else
cPtr->writeFR(cPtr, 0x05, tmp & 0xF7);
}
} else {
tmp = cPtr->readXR(cPtr, 0x52);
if (lcdoff)
cPtr->writeXR(cPtr, 0x52, tmp | 0x08);
else
cPtr->writeXR(cPtr, 0x52, tmp & 0xF7);
}
}
}
static Bool
CHIPSSaveScreen(ScreenPtr pScreen, int mode)
{
ScrnInfoPtr pScrn = NULL;
Bool unblank;
unblank = xf86IsUnblank(mode);
if (pScreen != NULL)
pScrn = xf86Screens[pScreen->myNum];
if (unblank)
SetTimeSinceLastInputEvent();
if ((pScrn != NULL) && pScrn->vtSema) {
chipsBlankScreen(pScrn, unblank);
}
return (TRUE);
}
static Bool
chipsClockSelect(ScrnInfoPtr pScrn, int no)
{
CHIPSClockReg TmpClock;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
switch (no) {
case CLK_REG_SAVE:
chipsClockSave(pScrn, &cPtr->SaveClock);
break;
case CLK_REG_RESTORE:
chipsClockLoad(pScrn, &cPtr->SaveClock);
break;
default:
if (!chipsClockFind(pScrn, no, &TmpClock))
return (FALSE);
chipsClockLoad(pScrn, &TmpClock);
}
return (TRUE);
}
static void
chipsClockSave(ScrnInfoPtr pScrn, CHIPSClockPtr Clock)
{
unsigned char tmp;
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char Type = cPtr->ClockType;
CHIPSEntPtr cPtrEnt;
Clock->msr = hwp->readMiscOut(hwp)&0xFE;
switch (Type & GET_STYLE) {
case HiQV_STYLE:
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
if (cPtr->Flags & ChipsDualChannelSupport)
Clock->fr03 = cPtr->readFR(cPtr, 0x01);
else
Clock->fr03 = cPtr->readFR(cPtr, 0x03);
if (!Clock->Clock) {
tmp = cPtr->CRTclkInx << 2;
cPtr->CRTClk[0] = cPtr->readXR(cPtr, 0xC0 + tmp);
cPtr->CRTClk[1] = cPtr->readXR(cPtr, 0xC1 + tmp);
cPtr->CRTClk[2] = cPtr->readXR(cPtr, 0xC2 + tmp);
cPtr->CRTClk[3] = cPtr->readXR(cPtr, 0xC3 + tmp);
tmp = cPtr->FPclkInx << 2;
cPtr->FPClk[0] = cPtr->readXR(cPtr, 0xC0 + tmp);
cPtr->FPClk[1] = cPtr->readXR(cPtr, 0xC1 + tmp);
cPtr->FPClk[2] = cPtr->readXR(cPtr, 0xC2 + tmp);
cPtr->FPClk[3] = cPtr->readXR(cPtr, 0xC3 + tmp);
}
break;
case OLD_STYLE:
Clock->fcr = hwp->readFCR(hwp);
Clock->xr02 = cPtr->readXR(cPtr, 0x02);
Clock->xr54 = cPtr->readXR(cPtr, 0x54);
break;
case WINGINE_1_STYLE:
case WINGINE_2_STYLE:
break;
case NEW_STYLE:
Clock->xr54 = cPtr->readXR(cPtr, 0x54);
Clock->xr33 = cPtr->readXR(cPtr, 0x33);
break;
}
#ifdef DEBUG
ErrorF("saved \n");
#endif
}
static Bool
chipsClockFind(ScrnInfoPtr pScrn, int no, CHIPSClockPtr Clock)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char Type = cPtr->ClockType;
CHIPSEntPtr cPtrEnt;
if (no > (pScrn->numClocks - 1))
return (FALSE);
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
switch (Type & GET_STYLE) {
case HiQV_STYLE:
Clock->msr = cPtr->CRTclkInx << 2;
Clock->fr03 = cPtr->FPclkInx << 2;
Clock->Clock = pScrn->currentMode->Clock;
if (xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
Clock->FPClock = pScrn->currentMode->Clock;
} else
Clock->FPClock = cPtr->FPclock;
break;
case NEW_STYLE:
if (Type & TYPE_HW) {
Clock->msr = (no == 4 ? 3 << 2: (no & 0x01) << 2);
Clock->xr54 = Clock->msr;
Clock->xr33 = no > 1 ? 0x80 : 0;
} else {
Clock->msr = 3 << 2;
Clock->xr33 = 0;
Clock->xr54 = Clock->msr;
chipsSetPanelType(cPtr);
{
Bool fp_m;
if (cPtr->Options
&& xf86GetOptValBool(cPtr->Options, OPTION_FP_MODE, &fp_m)) {
if (fp_m)
cPtr->PanelType |= ChipsLCD;
else
cPtr->PanelType = ~ChipsLCD;
}
}
if ((cPtr->PanelType & ChipsLCD) && cPtr->FPclock)
Clock->Clock = cPtr->FPclock;
else
Clock->Clock = pScrn->currentMode->SynthClock;
}
break;
case OLD_STYLE:
if (no > 3) {
Clock->msr = 3 << 2;
Clock->fcr = no & 0x03;
Clock->xr02 = 0;
Clock->xr54 = Clock->msr & (Clock->fcr << 4);
} else {
Clock->msr = (no << 2) & 0x4;
Clock->fcr = 0;
Clock->xr02 = no & 0x02;
Clock->xr54 = Clock->msr;
}
break;
case WINGINE_1_STYLE:
Clock->msr = no << 2;
case WINGINE_2_STYLE:
if (Type & TYPE_HW) {
Clock->msr = (no == 2 ? 3 << 2: (no & 0x01) << 2);
Clock->xr33 = 0;
} else {
Clock->msr = 3 << 2;
Clock->xr33 = 0;
Clock->Clock = pScrn->currentMode->SynthClock;
}
break;
}
Clock->msr |= (hwp->readMiscOut(hwp) & 0xF2);
#ifdef DEBUG
ErrorF("found\n");
#endif
return (TRUE);
}
static int
chipsGetHWClock(ScrnInfoPtr pScrn)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char Type = cPtr->ClockType;
unsigned char tmp, tmp1;
if (!(Type & TYPE_HW))
return 0;
switch (Type & GET_STYLE) {
case WINGINE_1_STYLE:
return ((hwp->readMiscOut(hwp) & 0x0C) >> 2);
case WINGINE_2_STYLE:
tmp = ((hwp->readMiscOut(hwp) & 0x04) >> 2);
return (tmp > 2) ? 2 : tmp;
case OLD_STYLE:
if (!(cPtr->PanelType & ChipsLCDProbed))
tmp = hwp->readMiscOut(hwp);
else
tmp = cPtr->readXR(cPtr, 0x54);
if (tmp & 0x08) {
if (!(cPtr->PanelType & ChipsLCDProbed))
tmp = hwp->readFCR(hwp) & 0x03;
else
tmp = (tmp >> 4) & 0x03;
return (tmp + 4);
} else {
tmp = (tmp >> 2) & 0x01;
tmp1 = cPtr->readXR(cPtr, 0x02);
return (tmp + (tmp1 & 0x02));
}
case NEW_STYLE:
if (cPtr->PanelType & ChipsLCDProbed) {
tmp = cPtr->readXR(cPtr, 0x54);
} else
tmp = hwp->readMiscOut(hwp);
tmp = (tmp & 0x0C) >> 2;
if (tmp > 1) return 4;
tmp1 = cPtr->readXR(cPtr, 0x33);
tmp1 = (tmp1 & 0x80) >> 6;
return (tmp + tmp1);
default:
return (0);
}
}
static void
chipsClockLoad(ScrnInfoPtr pScrn, CHIPSClockPtr Clock)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char Type = cPtr->ClockType;
volatile unsigned char tmp, tmpmsr, tmpfcr, tmp02;
volatile unsigned char tmp33, tmp54, tmpf03;
unsigned char vclk[3];
tmpmsr = hwp->readMiscOut(hwp);
switch (Type & GET_STYLE) {
case HiQV_STYLE:
if (cPtr->Flags & ChipsDualChannelSupport) {
tmpf03 = cPtr->readFR(cPtr, 0x01);
} else
tmpf03 = cPtr->readFR(cPtr, 0x03);
hwp->writeMiscOut(hwp, (tmpmsr & ~0x0D) |
cPtr->SuspendHack.vgaIOBaseFlag);
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtr->writeFR(cPtr, 0x01, (tmpf03 & ~0x0C) | 0x04);
} else
cPtr->writeFR(cPtr, 0x03, (tmpf03 & ~0x0C) | 0x04);
if (!Clock->Clock) {
tmp = cPtr->CRTclkInx << 2;
cPtr->writeXR(cPtr, 0xC0 + tmp, (cPtr->CRTClk[0] & 0xFF));
cPtr->writeXR(cPtr, 0xC1 + tmp, (cPtr->CRTClk[1] & 0xFF));
cPtr->writeXR(cPtr, 0xC2 + tmp, (cPtr->CRTClk[2] & 0xFF));
cPtr->writeXR(cPtr, 0xC3 + tmp, (cPtr->CRTClk[3] & 0xFF));
if (cPtr->FPClkModified) {
usleep(10000);
tmp = cPtr->FPclkInx << 2;
cPtr->writeXR(cPtr, 0xC0 + tmp, (cPtr->FPClk[0] & 0xFF));
cPtr->writeXR(cPtr, 0xC1 + tmp, (cPtr->FPClk[1] & 0xFF));
cPtr->writeXR(cPtr, 0xC2 + tmp, (cPtr->FPClk[2] & 0xFF));
cPtr->writeXR(cPtr, 0xC3 + tmp, (cPtr->FPClk[3] & 0xFF));
}
} else {
chipsCalcClock(pScrn, Clock->Clock, vclk);
tmp = cPtr->CRTclkInx << 2;
cPtr->writeXR(cPtr, 0xC0 + tmp, (vclk[1] & 0xFF));
cPtr->writeXR(cPtr, 0xC1 + tmp, (vclk[2] & 0xFF));
cPtr->writeXR(cPtr, 0xC2 + tmp, 0x0);
cPtr->writeXR(cPtr, 0xC3 + tmp, (vclk[0] & 0xFF));
if (Clock->FPClock) {
usleep(10000);
chipsCalcClock(pScrn, Clock->FPClock, vclk);
tmp = cPtr->FPclkInx << 2;
cPtr->writeXR(cPtr, 0xC0 + tmp, (vclk[1] & 0xFF));
cPtr->writeXR(cPtr, 0xC1 + tmp, (vclk[2] & 0xFF));
cPtr->writeXR(cPtr, 0xC2 + tmp, 0x0);
cPtr->writeXR(cPtr, 0xC3 + tmp, (vclk[0] & 0xFF));
cPtr->FPClkModified = TRUE;
}
}
usleep(10000);
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtr->writeFR(cPtr, 0x01, ((tmpf03 & ~0x0C) |
(Clock->fr03 & 0x0C)));
} else
cPtr->writeFR(cPtr, 0x03, ((tmpf03 & ~0x0C) |
(Clock->fr03 & 0x0C)));
break;
case WINGINE_1_STYLE:
break;
case WINGINE_2_STYLE:
if ((Type & GET_TYPE) == TYPE_PROGRAMMABLE) {
hwp->writeMiscOut(hwp, (tmpmsr & ~0x0D) |
cPtr->SuspendHack.vgaIOBaseFlag);
chipsCalcClock(pScrn, Clock->Clock, vclk);
tmp33 = cPtr->readXR(cPtr, 0x33);
cPtr->writeXR(cPtr, 0x33, tmp33 & ~0x20);
cPtr->writeXR(cPtr, 0x30, vclk[0]);
cPtr->writeXR(cPtr, 0x31, vclk[1]);
cPtr->writeXR(cPtr, 0x32, vclk[2]);
usleep(10000);
}
break;
case OLD_STYLE:
tmp02 = cPtr->readXR(cPtr, 0x02);
tmp54 = cPtr->readXR(cPtr, 0x54);
tmpfcr = hwp->readFCR(hwp);
cPtr->writeXR(cPtr, 0x02, ((tmp02 & ~0x02) | (Clock->xr02 & 0x02)));
cPtr->writeXR(cPtr, 0x54, ((tmp54 & 0xF0) | (Clock->xr54 & ~0xF0)));
hwp->writeFCR(hwp, (tmpfcr & ~0x03) & Clock->fcr);
break;
case NEW_STYLE:
tmp33 = cPtr->readXR(cPtr, 0x33);
tmp54 = cPtr->readXR(cPtr, 0x54);
if ((Type & GET_TYPE) == TYPE_PROGRAMMABLE) {
hwp->writeMiscOut(hwp, (tmpmsr & ~0x0D) |
cPtr->SuspendHack.vgaIOBaseFlag);
cPtr->writeXR(cPtr, 0x54, (tmp54 & 0xF3));
if (cPtr->MemClock.Clk) {
chipsCalcClock(pScrn, cPtr->MemClock.Clk, vclk);
cPtr->writeXR(cPtr, 0x33, tmp33 | 0x20);
cPtr->writeXR(cPtr, 0x30, vclk[0]);
cPtr->writeXR(cPtr, 0x31, vclk[1]);
cPtr->writeXR(cPtr, 0x32, vclk[2]);
usleep(10000);
}
chipsCalcClock(pScrn, Clock->Clock, vclk);
cPtr->writeXR(cPtr, 0x33, tmp33 & ~0x20);
cPtr->writeXR(cPtr, 0x30, vclk[0]);
cPtr->writeXR(cPtr, 0x31, vclk[1]);
cPtr->writeXR(cPtr, 0x32, vclk[2]);
usleep(10000);
}
cPtr->writeXR(cPtr, 0x33, ((tmp33 & ~0x80) | (Clock->xr33 & 0x80)));
cPtr->writeXR(cPtr, 0x54, ((tmp54 & 0xF3) | (Clock->xr54 & ~0xF3)));
break;
}
hwp->writeMiscOut(hwp, (Clock->msr & 0xFE) |
cPtr->SuspendHack.vgaIOBaseFlag);
#ifdef DEBUG
ErrorF("restored\n");
#endif
}
static void
chipsCalcClock(ScrnInfoPtr pScrn, int Clock, unsigned char *vclk)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int M, N, P = 0, PSN = 0, PSNx = 0;
int bestM = 0, bestN = 0, bestP = 0, bestPSN = 0;
double abest = 42;
#ifdef DEBUG
double bestFout = 0;
#endif
double target;
double Fvco, Fout;
double error, aerror;
int M_min = 3;
int M_max = (IS_HiQV(cPtr) && cPtr->Chipset != CHIPS_CT69000 &&
cPtr->Chipset != CHIPS_CT69030) ? 63 : 127;
target = Clock * 1000;
for (PSNx = ((cPtr->Chipset == CHIPS_CT69000) ||
(cPtr->Chipset == CHIPS_CT69030)) ? 1 : 0; PSNx <= 1; PSNx++) {
int low_N, high_N;
double Fref4PSN;
PSN = PSNx ? 1 : 4;
low_N = 3;
high_N = 127;
while (Fref / (PSN * low_N) > (((cPtr->Chipset == CHIPS_CT69000) ||
(cPtr->Chipset == CHIPS_CT69030)) ? 5.0e6 : 2.0e6))
low_N++;
while (Fref / (PSN * high_N) < 150.0e3)
high_N--;
Fref4PSN = Fref * 4 / PSN;
for (N = low_N; N <= high_N; N++) {
double tmp = Fref4PSN / N;
for (P = (IS_HiQV(cPtr) && (cPtr->Chipset != CHIPS_CT69000) &&
(cPtr->Chipset != CHIPS_CT69030)) ? 1 : 0;
P <= 5; P++) {
double Fvco_desired = target * (1 << P);
double M_desired = Fvco_desired / tmp;
int M_low = M_desired - 1;
int M_hi = M_desired + 1;
if (M_hi < M_min || M_low > M_max)
continue;
if (M_low < M_min)
M_low = M_min;
if (M_hi > M_max)
M_hi = M_max;
for (M = M_low; M <= M_hi; M++) {
Fvco = tmp * M;
if (Fvco <= ((cPtr->Chipset == CHIPS_CT69000 ||
cPtr->Chipset == CHIPS_CT69030) ? 100.0e6 : 48.0e6))
continue;
if (Fvco > 220.0e6)
break;
Fout = Fvco / (1 << P);
error = (target - Fout) / target;
aerror = (error < 0) ? -error : error;
if (aerror < abest) {
abest = aerror;
bestM = M;
bestN = N;
bestP = P;
bestPSN = PSN;
#ifdef DEBUG
bestFout = Fout;
#endif
}
}
}
}
}
vclk[0] = (bestP << (IS_HiQV(cPtr) ? 4 : 1)) +
(((cPtr->Chipset == CHIPS_CT69000) || (cPtr->Chipset == CHIPS_CT69030))
? 0 : (bestPSN == 1));
vclk[1] = bestM - 2;
vclk[2] = bestN - 2;
#ifdef DEBUG
ErrorF("Freq. selected: %.2f MHz, vclk[0]=%X, vclk[1]=%X, vclk[2]=%X\n",
(float)(Clock / 1000.), vclk[0], vclk[1], vclk[2]);
ErrorF("Freq. set: %.2f MHz\n", bestFout / 1.0e6);
#endif
}
static void
chipsSave(ScrnInfoPtr pScrn, vgaRegPtr VgaSave, CHIPSRegPtr ChipsSave)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int i;
unsigned char tmp;
#ifdef DEBUG
ErrorF("chipsSave\n");
#endif
if (IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr, 0x0E, 0x00);
} else {
cPtr->writeXR(cPtr, 0x10, 0x00);
cPtr->writeXR(cPtr, 0x11, 0x00);
tmp = cPtr->readXR(cPtr, 0x0C) & ~0x50;
cPtr->writeXR(cPtr, 0x0C, tmp);
}
chipsFixResume(pScrn);
tmp = cPtr->readXR(cPtr, 0x02);
cPtr->writeXR(cPtr, 0x02, tmp & ~0x18);
vgaHWSave(pScrn, VgaSave, VGA_SR_ALL);
chipsClockSave(pScrn, &ChipsSave->Clock);
if (IS_HiQV(cPtr)) {
for (i = 0; i < 0xFF; i++) {
#ifdef SAR04
if (i == 0x4F)
cPtr->writeXR(cPtr, 0x4E, 0x04);
#endif
ChipsSave->XR[i] = cPtr->readXR(cPtr,i);
#ifdef DEBUG
ErrorF("XS%X - %X\n", i, ChipsSave->XR[i]);
#endif
}
for (i = 0; i < 0x80; i++) {
ChipsSave->FR[i] = cPtr->readFR(cPtr, i);
#ifdef DEBUG
ErrorF("FS%X - %X\n", i, ChipsSave->FR[i]);
#endif
}
for (i = 0; i < 0x80; i++) {
ChipsSave->MR[i] = cPtr->readMR(cPtr, i);
#ifdef DEBUG
ErrorF("MS%X - %X\n", i, ChipsSave->FR[i]);
#endif
}
for (i = 0x0; i < 0x80; i++) {
ChipsSave->CR[i] = hwp->readCrtc(hwp, i);
#ifdef DEBUG
ErrorF("CS%X - %X\n", i, ChipsSave->CR[i]);
#endif
}
} else {
for (i = 0; i < 0x7D; i++) {
ChipsSave->XR[i] = cPtr->readXR(cPtr, i);
#ifdef DEBUG
ErrorF("XS%X - %X\n", i, ChipsSave->XR[i]);
#endif
}
}
}
Bool
chipsModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
#ifdef DEBUG
ErrorF("chipsModeInit\n");
#endif
#if 0
*(int*)0xFFFFFF0 = 0;
ErrorF("done\n");
#endif
chipsUnlock(pScrn);
chipsFixResume(pScrn);
if (cPtr->Accel.UseHWCursor)
cPtr->Flags |= ChipsHWCursor;
else
cPtr->Flags &= ~ChipsHWCursor;
cPtr->cursorDelay = TRUE;
if (IS_HiQV(cPtr))
return chipsModeInitHiQV(pScrn, mode);
else if (IS_Wingine(cPtr))
return chipsModeInitWingine(pScrn, mode);
else
return chipsModeInit655xx(pScrn, mode);
}
static Bool
chipsModeInitHiQV(ScrnInfoPtr pScrn, DisplayModePtr mode)
{
int i;
int lcdHTotal, lcdHDisplay;
int lcdVTotal, lcdVDisplay;
int lcdHRetraceStart, lcdHRetraceEnd;
int lcdVRetraceStart, lcdVRetraceEnd;
int lcdHSyncStart;
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSRegPtr ChipsNew;
vgaRegPtr ChipsStd;
unsigned int tmp;
ChipsNew = &cPtr->ModeReg;
ChipsStd = &hwp->ModeReg;
if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
cPtr->PanelSize.HDisplay = mode->CrtcHDisplay;
cPtr->PanelSize.VDisplay = mode->CrtcVDisplay;
}
if (!vgaHWInit(pScrn, mode)) {
ErrorF("bomb 1\n");
return (FALSE);
}
pScrn->vtSema = TRUE;
if (!chipsClockFind(pScrn, mode->ClockIndex, &ChipsNew->Clock)) {
ErrorF("bomb 2\n");
return (FALSE);
}
if (cPtr->UseDualChannel && ((cPtr->SecondCrtc == TRUE) ||
(cPtr->Flags & ChipsDualRefresh))) {
if (((ChipsNew->Clock.FPClock + ChipsNew->Clock.Clock) *
(max(1, pScrn->bitsPerPixel >> 3) +
((cPtr->FrameBufferSize && (cPtr->PanelType & ChipsLCD)) ?
1 : 0)) / (8 * 0.7)) > cPtr->MemClock.Max) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Memory bandwidth requirements exceeded by dual-channel\n");
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
" mode. Display might be corrupted!!!\n");
}
}
for (i = 0; i < 0xFF; i++) {
#ifdef SAR04
if (i == 0x4F)
cPtr->writeXR(cPtr, 0x4E, 0x04);
#endif
ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
}
for (i = 0; i < 0x80; i++) {
ChipsNew->FR[i] = cPtr->readFR(cPtr, i);
}
for (i = 0; i < 0x80; i++) {
ChipsNew->MR[i] = cPtr->readMR(cPtr, i);
}
for (i = 0x30; i < 0x80; i++) {
ChipsNew->CR[i] = hwp->readCrtc(hwp, i);
}
if (pScrn->depth == 1) {
ChipsStd->Attribute[0x10] = 0x03;
} else {
ChipsStd->Attribute[0x10] = 0x01;
}
if ((pScrn->bitsPerPixel == 16) && (cPtr->Flags & ChipsOverlay8plus16)) {
if (ChipsStd->Attribute[0x11] == pScrn->colorKey)
ChipsStd->Attribute[0x11] = pScrn->colorKey - 1;
} else
ChipsStd->Attribute[0x11] = 0x00;
ChipsStd->Attribute[0x12] = 0x0F;
ChipsStd->Attribute[0x13] = 0x00;
ChipsStd->Graphics[0x05] = 0x00;
tmp = pScrn->displayWidth >> 3;
if (pScrn->bitsPerPixel == 16) {
if (!(cPtr->Flags & ChipsOverlay8plus16))
tmp <<= 1;
} else if (pScrn->bitsPerPixel == 24) {
tmp += tmp << 1;
} else if (pScrn->bitsPerPixel == 32) {
tmp <<= 2;
} else if (pScrn->bitsPerPixel < 8) {
tmp >>= 1;
}
ChipsStd->CRTC[0x13] = tmp & 0xFF;
ChipsNew->CR[0x41] = (tmp >> 8) & 0x0F;
if (!(cPtr->Flags & ChipsLinearSupport) || (pScrn->bitsPerPixel < 8))
ChipsNew->XR[0x0A] |= 0x1;
ChipsNew->XR[0x09] |= 0x1;
ChipsNew->XR[0x0E] = 0;
ChipsNew->XR[0x40] |= 0x2;
ChipsNew->XR[0x81] &= 0xF8;
if (pScrn->bitsPerPixel >= 8) {
ChipsNew->XR[0x40] |= 0x1;
ChipsNew->XR[0x81] |= 0x2;
}
ChipsNew->XR[0x80] |= 0x10;
if (pScrn->depth > 1) {
if (pScrn->rgbBits == 8)
ChipsNew->XR[0x80] |= 0x80;
else
ChipsNew->XR[0x80] &= ~0x80;
}
if (abs(cPtr->MemClock.Clk - cPtr->MemClock.ProbedClk) > 50) {
ChipsNew->XR[0xCC] = cPtr->MemClock.xrCC;
ChipsNew->XR[0xCD] = cPtr->MemClock.xrCD;
ChipsNew->XR[0xCE] = cPtr->MemClock.xrCE;
}
if (cPtr->Flags & ChipsDualChannelSupport) {
ChipsNew->FR[0x01] &= 0xFC;
if ((cPtr->SecondCrtc == FALSE) && (cPtr->PanelType & ChipsLCD))
ChipsNew->FR[0x01] |= 0x02;
else
ChipsNew->FR[0x01] |= 0x01;
ChipsNew->FR[0x02] &= 0xCC;
if ((cPtr->SecondCrtc == TRUE) || (cPtr->Flags & ChipsDualRefresh))
ChipsNew->FR[0x02] |= 0x01;
else
ChipsNew->FR[0x02] &= 0xFE;
if (cPtr->PanelType & ChipsLCD)
ChipsNew->FR[0x02] |= 0x20;
if (cPtr->PanelType & ChipsCRT)
ChipsNew->FR[0x02] |= 0x10;
}
if (cPtr->Flags & ChipsLinearSupport) {
ChipsNew->XR[0x0A] |= 0x02;
ChipsNew->XR[0x20] = 0x0;
ChipsNew->XR[0x05] =
(unsigned char)((cPtr->FbAddress >> 16) & 0xFF);
ChipsNew->XR[0x06] =
(unsigned char)((cPtr->FbAddress >> 24) & 0xFF);
}
if (xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
lcdHTotal = (mode->CrtcHTotal >> 3) - 5;
lcdHDisplay = (cPtr->PanelSize.HDisplay >> 3) - 1;
lcdHRetraceStart = (mode->CrtcHSyncStart >> 3);
lcdHRetraceEnd = (mode->CrtcHSyncEnd >> 3);
lcdHSyncStart = lcdHRetraceStart - 2;
lcdVTotal = mode->CrtcVTotal - 2;
lcdVDisplay = cPtr->PanelSize.VDisplay - 1;
lcdVRetraceStart = mode->CrtcVSyncStart;
lcdVRetraceEnd = mode->CrtcVSyncEnd;
ChipsNew->FR[0x20] = lcdHDisplay & 0xFF;
ChipsNew->FR[0x21] = lcdHRetraceStart & 0xFF;
ChipsNew->FR[0x25] = ((lcdHRetraceStart & 0xF00) >> 4) |
((lcdHDisplay & 0xF00) >> 8);
ChipsNew->FR[0x22] = lcdHRetraceEnd & 0x1F;
ChipsNew->FR[0x23] = lcdHTotal & 0xFF;
ChipsNew->FR[0x24] = (lcdHSyncStart >> 3) & 0xFF;
ChipsNew->FR[0x26] = (ChipsNew->FR[0x26] & ~0x1F)
| ((lcdHTotal & 0xF00) >> 8)
| (((lcdHSyncStart >> 3) & 0x100) >> 4);
ChipsNew->FR[0x27] &= 0x7F;
ChipsNew->FR[0x30] = lcdVDisplay & 0xFF;
ChipsNew->FR[0x31] = lcdVRetraceStart & 0xFF;
ChipsNew->FR[0x35] = ((lcdVRetraceStart & 0xF00) >> 4)
| ((lcdVDisplay & 0xF00) >> 8);
ChipsNew->FR[0x32] = lcdVRetraceEnd & 0x0F;
ChipsNew->FR[0x33] = lcdVTotal & 0xFF;
ChipsNew->FR[0x34] = (lcdVTotal - lcdVRetraceStart) & 0xFF;
ChipsNew->FR[0x36] = ((lcdVTotal & 0xF00) >> 8) |
(((lcdVTotal - lcdVRetraceStart) & 0x700) >> 4);
ChipsNew->FR[0x37] |= 0x80;
}
ChipsNew->CR[0x30] = ((mode->CrtcVTotal - 2) & 0xF00) >> 8;
ChipsNew->CR[0x31] = ((mode->CrtcVDisplay - 1) & 0xF00) >> 8;
ChipsNew->CR[0x32] = (mode->CrtcVSyncStart & 0xF00) >> 8;
ChipsNew->CR[0x33] = (mode->CrtcVBlankStart & 0xF00) >> 8;
if ((cPtr->Chipset == CHIPS_CT69000) || (cPtr->Chipset == CHIPS_CT69030)) {
ChipsNew->CR[0x38] = (((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8;
#if 0
ChipsStd->CRTC[3] = (ChipsStd->CRTC[3] & ~0x1F)
| (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F);
ChipsStd->CRTC[5] = (ChipsStd->CRTC[5] & ~0x80)
| ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2);
ChipsNew->CR[0x3C] = ((mode->CrtcHBlankEnd >> 3) - 1) & 0xC0;
if ((mode->CrtcHBlankEnd >> 3) == (mode->CrtcHTotal >> 3)) {
int i = (ChipsStd->CRTC[3] & 0x1F)
| ((ChipsStd->CRTC[5] & 0x80) >> 2)
| (ChipsNew->CR[0x3C] & 0xC0);
if ((i-- > (ChipsStd->CRTC[2])) &&
(mode->CrtcHBlankEnd == mode->CrtcHTotal))
i = 0;
ChipsStd->CRTC[3] = (ChipsStd->CRTC[3] & ~0x1F) | (i & 0x1F);
ChipsStd->CRTC[5] = (ChipsStd->CRTC[5] & ~0x80) | ((i << 2) &0x80);
ChipsNew->CR[0x3C] = (i & 0xC0);
}
#else
ChipsNew->CR[0x3C] = vgaHWHBlankKGA(mode, ChipsStd, 8, 0) << 6;
#endif
} else
vgaHWHBlankKGA(mode, ChipsStd, 6, 0);
vgaHWVBlankKGA(mode, ChipsStd, 8, 0);
ChipsNew->CR[0x40] |= 0x80;
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_SUSPEND_HACK, FALSE)) {
if (xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_STRETCH, FALSE) ||
(cPtr->Flags & ChipsOverlay8plus16)) {
ChipsNew->FR[0x40] &= 0xDF;
ChipsNew->FR[0x48] &= 0xFB;
ChipsNew->XR[0xA0] = 0x10;
} else {
ChipsNew->FR[0x40] |= 0x21;
ChipsNew->FR[0x48] |= 0x05;
ChipsNew->XR[0xA0] = 0x70;
if (cPtr->Accel.UseHWCursor
&& cPtr->PanelSize.HDisplay && cPtr->PanelSize.VDisplay
&& (cPtr->PanelSize.HDisplay != mode->CrtcHDisplay)
&& (cPtr->PanelSize.VDisplay != mode->CrtcVDisplay)) {
if(cPtr->Accel.UseHWCursor)
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Disabling HW Cursor on stretched LCD\n");
cPtr->Flags &= ~ChipsHWCursor;
}
}
}
if ((xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_CENTER, FALSE))
|| (cPtr->Flags & ChipsOverlay8plus16)) {
ChipsNew->FR[0x40] |= 0x3;
ChipsNew->FR[0x48] |= 0x3;
} else {
ChipsNew->FR[0x40] &= 0xFD;
ChipsNew->FR[0x48] &= 0xFD;
}
if (xf86ReturnOptValBool(cPtr->Options, OPTION_SYNC_ON_GREEN, FALSE))
ChipsNew->XR[0x82] |=0x02;
ChipsNew->XR[0xE2] = chipsVideoMode(((cPtr->Flags & ChipsOverlay8plus16) ?
8 : pScrn->depth), (cPtr->PanelType & ChipsLCD) ?
min(mode->CrtcHDisplay, cPtr->PanelSize.HDisplay) :
mode->CrtcHDisplay, mode->CrtcVDisplay);
#ifdef DEBUG
ErrorF("VESA Mode: %Xh\n", ChipsNew->XR[0xE2]);
#endif
if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
&& (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
if (mode->Flags & (V_PHSYNC | V_NHSYNC)) {
if (mode->Flags & V_PHSYNC)
ChipsNew->FR[0x08] &= 0xBF;
else
ChipsNew->FR[0x08] |= 0x40;
}
if (mode->Flags & (V_PVSYNC | V_NVSYNC)) {
if (mode->Flags & V_PVSYNC)
ChipsNew->FR[0x08] &= 0x7F;
else
ChipsNew->FR[0x08] |= 0x80;
}
}
if (mode->Flags & (V_PCSYNC | V_NCSYNC)) {
ChipsNew->FR[0x0B] |= 0x20;
if (mode->Flags & V_PCSYNC) {
ChipsNew->FR[0x08] &= 0x7F;
ChipsNew->FR[0x08] &= 0xBF;
ChipsStd->MiscOutReg &= 0x7F;
ChipsStd->MiscOutReg &= 0xBF;
} else {
ChipsNew->FR[0x08] |= 0x80;
ChipsNew->FR[0x08] |= 0x40;
ChipsStd->MiscOutReg |= 0x40;
ChipsStd->MiscOutReg |= 0x80;
}
}
if ((pScrn->bitsPerPixel == 16) && (!(cPtr->Flags & ChipsOverlay8plus16))) {
ChipsNew->XR[0x81] = (ChipsNew->XR[0x81] & 0xF0) | 0x4;
if (cPtr->Flags & ChipsGammaSupport)
ChipsNew->XR[0x82] |= 0x0C;
ChipsNew->FR[0x10] |= 0x0C;
ChipsNew->XR[0x20] = 0x10;
if (pScrn->weight.green != 5)
ChipsNew->XR[0x81] |= 0x01;
} else if (pScrn->bitsPerPixel == 24) {
ChipsNew->XR[0x81] = (ChipsNew->XR[0x81] & 0xF0) | 0x6;
if (cPtr->Flags & ChipsGammaSupport)
ChipsNew->XR[0x82] |= 0x0C;
ChipsNew->XR[0x20] = 0x20;
} else if (pScrn->bitsPerPixel == 32) {
ChipsNew->XR[0x81] = (ChipsNew->XR[0x81] & 0xF0) | 0x7;
if (cPtr->Flags & ChipsGammaSupport)
ChipsNew->XR[0x82] |= 0x0C;
ChipsNew->XR[0x20] = 0x10;
}
if (!(cPtr->PanelType & ChipsLCD)) {
if (mode->Flags & V_INTERLACE) {
ChipsNew->CR[0x70] = 0x80
| (((((mode->CrtcHDisplay >> 3) - 1) >> 1) - 6) & 0x7F);
mode->CrtcVDisplay = mode->VDisplay;
tmp = ChipsStd->CRTC[7] & ~0x42;
ChipsStd->CRTC[7] = (tmp |
((((mode->CrtcVDisplay -1) & 0x100) >> 7 ) |
(((mode->CrtcVDisplay -1) & 0x200) >> 3 )));
ChipsStd->CRTC[0x12] = (mode->CrtcVDisplay -1) & 0xFF;
ChipsNew->CR[0x31] = ((mode->CrtcVDisplay - 1) & 0xF00) >> 8;
} else {
ChipsNew->CR[0x70] &= ~0x80;
}
}
#if defined(__arm32__) && defined(__NetBSD__)
if (cPtr->TVMode != XMODE_RGB) {
xf86SetTVOut(cPtr->TVMode);
ChipsNew->CR[0x72] = (mode->CrtcHTotal >> 1) >> 3;
ChipsNew->CR[0x73] = mode->CrtcHTotal >> 3;
ChipsNew->CR[0x74] = (((mode->HSyncEnd - mode->HSyncStart) >> 3) - 1)
& 0x1F;
if (cPtr->TVMode == XMODE_PAL || cPtr->TVMode == XMODE_SECAM) {
ChipsNew->CR[0x71] = 0xA0;
} else {
ChipsNew->CR[0x71] = 0x20;
}
} else {
xf86SetRGBOut();
}
#endif
if (IS_STN(cPtr->PanelType)) {
ChipsNew->FR[0x11] &= ~0x03;
ChipsNew->FR[0x11] &= ~0x8C;
ChipsNew->FR[0x11] |= 0x01;
ChipsNew->FR[0x11] |= 0x84;
if ((cPtr->Flags & ChipsTMEDSupport) &&
!xf86ReturnOptValBool(cPtr->Options, OPTION_NO_TMED, FALSE)) {
ChipsNew->FR[0x73] &= 0x4F;
ChipsNew->FR[0x73] |= 0x80;
ChipsNew->FR[0x73] |= 0x30;
}
if (cPtr->PanelType & ChipsDD)
ChipsNew->FR[0x12] |= 0x4;
}
if (cPtr->PanelType & ChipsLCD) {
cPtr->OverlaySkewX = (((ChipsNew->FR[0x23] & 0xFF)
- (ChipsNew->FR[0x20] & 0xFF) + 3) << 3)
- 1;
cPtr->OverlaySkewY = (ChipsNew->FR[0x33]
+ ((ChipsNew->FR[0x36] & 0xF) << 8)
- (ChipsNew->FR[0x31] & 0xF0)
- (ChipsNew->FR[0x32] & 0x0F)
- ((ChipsNew->FR[0x35] & 0xF0) << 4));
if (cPtr->PanelSize.HDisplay > mode->CrtcHDisplay)
cPtr->OverlaySkewX += (cPtr->PanelSize.HDisplay -
mode->CrtcHDisplay) / 2;
if (cPtr->PanelSize.VDisplay > mode->CrtcVDisplay)
cPtr->OverlaySkewY += (cPtr->PanelSize.VDisplay -
mode->CrtcVDisplay) / 2;
} else {
cPtr->OverlaySkewX = mode->CrtcHTotal - mode->CrtcHBlankStart - 9;
cPtr->OverlaySkewY = mode->CrtcVTotal - mode->CrtcVSyncEnd - 1;
if (mode->Flags & V_INTERLACE) {
#if 0
if (mode->CrtcHDisplay == 1024)
cPtr->OverlaySkewY += 5;
else if (mode->CrtcHDisplay == 1280)
#endif
cPtr->OverlaySkewY *= 2;
}
}
switch (pScrn->bitsPerPixel) {
case 8:
cPtr->viewportMask = ~7U;
break;
case 16:
cPtr->viewportMask = ~3U;
break;
case 24:
cPtr->viewportMask = ~7U;
break;
case 32:
cPtr->viewportMask = ~0U;
break;
default:
cPtr->viewportMask = ~7U;
}
ChipsNew->XR[0xD0] &= 0x0f;
if (cPtr->Flags & ChipsOverlay8plus16) {
ChipsNew->XR[0xD0] |= 0x10;
#ifdef SAR04
ChipsNew->XR[0x4F] = 0x2A;
#endif
ChipsNew->MR[0x1E] &= 0xE0;
if ((!(cPtr->PanelType & ChipsLCD)) && (mode->Flags & V_INTERLACE))
ChipsNew->MR[0x1E] |= 0x10;
ChipsNew->MR[0x1F] &= 0x14;
ChipsNew->MR[0x1F] |= 0x08;
if (pScrn->weight.green == 5)
ChipsNew->MR[0x1F] |= 0x01;
ChipsNew->MR[0x20] &= 0x03;
ChipsNew->MR[0x20] |= 0x80;
ChipsNew->MR[0x22] = cPtr->FbOffset16 & 0xF8;
ChipsNew->MR[0x23] = (cPtr->FbOffset16 >> 8) & 0xFF;
ChipsNew->MR[0x24] = (cPtr->FbOffset16 >> 16) & 0xFF;
ChipsNew->MR[0x25] = cPtr->FbOffset16 & 0xF8;
ChipsNew->MR[0x26] = (cPtr->FbOffset16 >> 8) & 0xFF;
ChipsNew->MR[0x27] = (cPtr->FbOffset16 >> 16) & 0xFF;
ChipsNew->MR[0x28] = (pScrn->displayWidth >> 2) - 1;
ChipsNew->MR[0x34] = (pScrn->displayWidth >> 2) - 1;
ChipsNew->MR[0x2A] = cPtr->OverlaySkewX;
ChipsNew->MR[0x2B] &= 0xF8;
ChipsNew->MR[0x2B] |= ((cPtr->OverlaySkewX >> 8) & 0x7);
ChipsNew->MR[0x2C] = (cPtr->OverlaySkewX + pScrn->displayWidth -
1) & 0xFF;
ChipsNew->MR[0x2D] &= 0xF8;
ChipsNew->MR[0x2D] |= ((cPtr->OverlaySkewX + pScrn->displayWidth -
1) >> 8) & 0x07;
ChipsNew->MR[0x2E] = cPtr->OverlaySkewY;
ChipsNew->MR[0x2F] &= 0xF8;
ChipsNew->MR[0x2F] |= ((cPtr->OverlaySkewY >> 8) & 0x7);
ChipsNew->MR[0x30] = (cPtr->OverlaySkewY + pScrn->virtualY - 1 )& 0xFF;
ChipsNew->MR[0x31] &= 0xF8;
ChipsNew->MR[0x31] |= ((cPtr->OverlaySkewY + pScrn->virtualY -
1 ) >> 8) & 0x07;
ChipsNew->MR[0x3C] &= 0x18;
ChipsNew->MR[0x3C] |= 0x07;
ChipsNew->MR[0x3D] = 0x00;
ChipsNew->MR[0x3E] = 0x00;
ChipsNew->MR[0x3F] = pScrn->colorKey;
ChipsNew->MR[0x40] = 0xFF;
ChipsNew->MR[0x41] = 0xFF;
ChipsNew->MR[0x42] = 0x00;
} else if (cPtr->Flags & ChipsVideoSupport) {
#if 0
ChipsNew->XR[0xD0] |= 0x10;
#endif
#ifdef SAR04
ChipsNew->XR[0x4F] = 0x2A;
#endif
ChipsNew->MR[0x3C] &= 0x18;
cPtr->VideoZoomMax = 0x100;
if (cPtr->Chipset == CHIPS_CT65550) {
tmp = cPtr->readXR(cPtr, 0x04);
if (tmp < 0x02)
cPtr->VideoZoomMax = 0x40;
}
}
if (cPtr->Chipset <= CHIPS_CT69000) {
ChipsNew->FR[0x01] &= ~0x03;
if (cPtr->PanelType & ChipsLCD)
ChipsNew->FR[0x01] |= 0x02;
else
ChipsNew->FR[0x01] |= 0x01;
}
if ((cPtr->Flags & ChipsDualChannelSupport) &&
(!xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned char IOSS, MSS, tmpfr01;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_A));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) |
MSS_PIPE_A));
chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) |
MSS_PIPE_B));
tmpfr01 = ChipsNew->FR[0x01];
ChipsNew->FR[0x01] &= 0xFC;
if (cPtr->UseDualChannel)
ChipsNew->FR[0x01] |= 0x01;
chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
ChipsNew->FR[0x01] = tmpfr01;
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
} else {
chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
}
usleep(100000);
return(TRUE);
}
static Bool
chipsModeInitWingine(ScrnInfoPtr pScrn, DisplayModePtr mode)
{
int i, bytesPerPixel;
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSRegPtr ChipsNew;
vgaRegPtr ChipsStd;
unsigned int tmp;
ChipsNew = &cPtr->ModeReg;
ChipsStd = &hwp->ModeReg;
bytesPerPixel = pScrn->bitsPerPixel >> 3;
if (!mode->CrtcHAdjusted)
mode->CrtcHBlankEnd = min(mode->CrtcHSyncEnd, mode->CrtcHTotal - 2);
if (pScrn->bitsPerPixel == 16) {
if (!mode->CrtcHAdjusted) {
mode->CrtcHDisplay++;
mode->CrtcHDisplay <<= 1;
mode->CrtcHDisplay--;
mode->CrtcHSyncStart <<= 1;
mode->CrtcHSyncEnd <<= 1;
mode->CrtcHBlankStart <<= 1;
mode->CrtcHBlankEnd <<= 1;
mode->CrtcHTotal <<= 1;
mode->CrtcHAdjusted = TRUE;
}
} else if (pScrn->bitsPerPixel == 24) {
if (!mode->CrtcHAdjusted) {
mode->CrtcHDisplay++;
mode->CrtcHDisplay += ((mode->CrtcHDisplay) << 1);
mode->CrtcHDisplay--;
mode->CrtcHSyncStart += ((mode->CrtcHSyncStart) << 1);
mode->CrtcHSyncEnd += ((mode->CrtcHSyncEnd) << 1);
mode->CrtcHBlankStart += ((mode->CrtcHBlankStart) << 1);
mode->CrtcHBlankEnd += ((mode->CrtcHBlankEnd) << 1);
mode->CrtcHTotal += ((mode->CrtcHTotal) << 1);
mode->CrtcHAdjusted = TRUE;
}
}
if (!vgaHWInit(pScrn, mode)) {
ErrorF("bomb 3\n");
return (FALSE);
}
pScrn->vtSema = TRUE;
if (!chipsClockFind(pScrn, mode->ClockIndex, &ChipsNew->Clock)) {
ErrorF("bomb 4\n");
return (FALSE);
}
for (i = 0; i < 0x7D; i++) {
ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
}
if (pScrn->bitsPerPixel == 1) {
ChipsStd->Attribute[0x10] = 0x03;
} else {
ChipsStd->Attribute[0x10] = 0x01;
}
ChipsStd->Attribute[0x11] = 0x00;
ChipsStd->Attribute[0x12] = 0x0F;
ChipsStd->Attribute[0x13] = 0x00;
ChipsStd->Graphics[0x05] = 0x00;
if (pScrn->bitsPerPixel >= 8)
ChipsStd->CRTC[0x13] = (pScrn->displayWidth * bytesPerPixel) >> 3;
else
ChipsStd->CRTC[0x13] = pScrn->displayWidth >> 4;
if (pScrn->bitsPerPixel >= 8)
tmp = (pScrn->displayWidth >> 4) * bytesPerPixel;
else
tmp = (pScrn->displayWidth >> 5);
ChipsNew->XR[0x0D] = (tmp & 0x80) >> 5;
ChipsNew->XR[0x04] |= 4;
ChipsNew->XR[0x0B] |= 0x07;
ChipsNew->XR[0x0B] &= ~0x10;
ChipsNew->XR[0x10] = 0;
ChipsNew->XR[0x11] = 0;
ChipsNew->XR[0x0C] &= ~0x50;
if (pScrn->bitsPerPixel >= 8) {
ChipsNew->XR[0x28] |= 0x10;
} else {
ChipsNew->XR[0x28] &= 0xEF;
}
ChipsNew->XR[0x17] = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8)
| ((((mode->CrtcHDisplay >> 3) - 1) & 0x100) >> 7)
| ((((mode->CrtcHSyncStart >> 3) - 1) & 0x100) >> 6)
| ((((mode->CrtcHSyncEnd >> 3)) & 0x20) >> 2)
| ((((mode->CrtcHBlankStart >> 3) - 1) & 0x100) >> 4)
| ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x40) >> 1);
ChipsNew->XR[0x16] = (((mode->CrtcVTotal -2) & 0x400) >> 10 )
| (((mode->CrtcVDisplay -1) & 0x400) >> 9 )
| ((mode->CrtcVSyncStart & 0x400) >> 8 )
| (((mode->CrtcVBlankStart) & 0x400) >> 6 );
ChipsNew->XR[0x2B] = chipsVideoMode(pScrn->depth, mode->CrtcHDisplay, mode->CrtcVDisplay);
#ifdef DEBUG
ErrorF("VESA Mode: %Xh\n", ChipsNew->XR[0x2B]);
#endif
if (cPtr->Flags & ChipsLinearSupport) {
ChipsNew->XR[0x0B] &= 0xFD;
ChipsNew->XR[0x0B] |= 0x10;
ChipsNew->XR[0x08] =
(unsigned char)((cPtr->FbAddress >> 16) & 0xFF);
ChipsNew->XR[0x09] =
(unsigned char)((cPtr->FbAddress >> 24) & 0xFF);
ChipsNew->XR[0x40] = 0x01;
}
ChipsNew->XR[0x52] |= 0x01;
ChipsNew->XR[0x0F] &= 0xEF;
ChipsNew->XR[0x02] &= 0xE7;
ChipsNew->XR[0x06] &= 0xF3;
if (pScrn->bitsPerPixel == 16) {
ChipsNew->XR[0x06] |= 0xC4;
ChipsNew->XR[0x0F] |= 0x10;
ChipsNew->XR[0x40] = 0x02;
if (pScrn->weight.green != 5)
ChipsNew->XR[0x06] |= 0x08;
} else if (pScrn->bitsPerPixel == 24) {
ChipsNew->XR[0x06] |= 0xC8;
ChipsNew->XR[0x0F] |= 0x10;
}
if (mode->Flags & V_INTERLACE) {
ChipsNew->XR[0x28] |= 0x20;
tmp = ((((mode->CrtcHDisplay >> 3) - 1) >> 1)
- 6 * (pScrn->bitsPerPixel >= 8 ? bytesPerPixel : 1 ));
ChipsNew->XR[0x19] = tmp & 0xFF;
ChipsNew->XR[0x17] |= ((tmp & 0x100) >> 1);
ChipsNew->XR[0x0F] &= ~0x40;
} else {
ChipsNew->XR[0x28] &= ~0x20;
ChipsNew->XR[0x0F] |= 0x40;
}
chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
return (TRUE);
}
static Bool
chipsModeInit655xx(ScrnInfoPtr pScrn, DisplayModePtr mode)
{
int i, bytesPerPixel;
int lcdHTotal, lcdHDisplay;
int lcdVTotal, lcdVDisplay;
int lcdHRetraceStart, lcdHRetraceEnd;
int lcdVRetraceStart, lcdVRetraceEnd;
int HSyncStart, HDisplay;
int CrtcHDisplay;
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
CHIPSRegPtr ChipsNew;
vgaRegPtr ChipsStd;
unsigned int tmp;
ChipsNew = &cPtr->ModeReg;
ChipsStd = &hwp->ModeReg;
bytesPerPixel = pScrn->bitsPerPixel >> 3;
if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
cPtr->PanelSize.HDisplay = mode->CrtcHDisplay;
cPtr->PanelSize.VDisplay = mode->CrtcVDisplay;
}
if (!mode->CrtcHAdjusted)
mode->CrtcHBlankEnd = min(mode->CrtcHSyncEnd, mode->CrtcHTotal - 2);
if (pScrn->bitsPerPixel == 16) {
if (!mode->CrtcHAdjusted) {
mode->CrtcHDisplay++;
mode->CrtcHDisplay <<= 1;
mode->CrtcHDisplay--;
mode->CrtcHSyncStart <<= 1;
mode->CrtcHSyncEnd <<= 1;
mode->CrtcHBlankStart <<= 1;
mode->CrtcHBlankEnd <<= 1;
mode->CrtcHTotal <<= 1;
mode->CrtcHAdjusted = TRUE;
}
} else if (pScrn->bitsPerPixel == 24) {
if (!mode->CrtcHAdjusted) {
mode->CrtcHDisplay++;
mode->CrtcHDisplay += ((mode->CrtcHDisplay) << 1);
mode->CrtcHDisplay--;
mode->CrtcHSyncStart += ((mode->CrtcHSyncStart) << 1);
mode->CrtcHSyncEnd += ((mode->CrtcHSyncEnd) << 1);
mode->CrtcHBlankStart += ((mode->CrtcHBlankStart) << 1);
mode->CrtcHBlankEnd += ((mode->CrtcHBlankEnd) << 1);
mode->CrtcHTotal += ((mode->CrtcHTotal) << 1);
mode->CrtcHAdjusted = TRUE;
}
}
HSyncStart = mode->CrtcHSyncStart / (pScrn->bitsPerPixel >= 8 ?
bytesPerPixel : 1 ) - 16;
HDisplay = (mode->CrtcHDisplay + 1) / (pScrn->bitsPerPixel >= 8 ?
bytesPerPixel : 1 );
if (!vgaHWInit(pScrn, mode)) {
ErrorF("bomb 5\n");
return (FALSE);
}
pScrn->vtSema = TRUE;
if (!chipsClockFind(pScrn, mode->ClockIndex, &ChipsNew->Clock)) {
ErrorF("bomb 6\n");
return (FALSE);
}
for (i = 0; i < 0x80; i++) {
ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
}
if (pScrn->bitsPerPixel == 1) {
ChipsStd->Attribute[0x10] = 0x03;
} else {
ChipsStd->Attribute[0x10] = 0x01;
}
ChipsStd->Attribute[0x11] = 0x00;
ChipsStd->Attribute[0x12] = 0x0F;
ChipsStd->Attribute[0x13] = 0x00;
ChipsStd->Graphics[0x05] = 0x00;
if (pScrn->bitsPerPixel >= 8)
ChipsStd->CRTC[0x13] = (pScrn->displayWidth * bytesPerPixel) >> 3;
else
ChipsStd->CRTC[0x13] = pScrn->displayWidth >> 4;
ChipsNew->XR[0x1E] = ChipsStd->CRTC[0x13];
if (pScrn->bitsPerPixel >= 8)
tmp = (pScrn->displayWidth * bytesPerPixel) >> 2;
else
tmp = pScrn->displayWidth >> 3;
ChipsNew->XR[0x0D] = (tmp & 0x01) | ((tmp << 1) & 0x02) ;
ChipsNew->XR[0x04] |= 4;
ChipsNew->XR[0x0B] |= 0x07;
ChipsNew->XR[0x0B] &= ~0x10;
ChipsNew->XR[0x10] = 0;
ChipsNew->XR[0x11] = 0;
if (pScrn->bitsPerPixel >= 8) {
ChipsNew->XR[0x28] |= 0x10;
} else {
ChipsNew->XR[0x28] &= 0xEF;
}
if (!(cPtr->PanelType & ChipsLCD)) {
ChipsNew->XR[0x17] = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8)
| ((((mode->CrtcHDisplay >> 3) - 1) & 0x100) >> 7)
| ((((mode->CrtcHSyncStart >> 3) - 1) & 0x100) >> 6)
| ((((mode->CrtcHSyncEnd >> 3)) & 0x20) >> 2)
| ((((mode->CrtcHBlankStart >> 3) - 1) & 0x100) >> 4)
| ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x40) >> 1);
ChipsNew->XR[0x16] = (((mode->CrtcVTotal -2) & 0x400) >> 10 )
| (((mode->CrtcVDisplay -1) & 0x400) >> 9 )
| ((mode->CrtcVSyncStart & 0x400) >> 8 )
| (((mode->CrtcVBlankStart) & 0x400) >> 6 );
} else {
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
lcdHTotal = cPtr->PanelSize.HTotal;
lcdHRetraceStart = cPtr->PanelSize.HRetraceStart;
lcdHRetraceEnd = cPtr->PanelSize.HRetraceEnd;
if (pScrn->bitsPerPixel == 16) {
lcdHRetraceStart <<= 1;
lcdHRetraceEnd <<= 1;
lcdHTotal <<= 1;
} else if (pScrn->bitsPerPixel == 24) {
lcdHRetraceStart += (lcdHRetraceStart << 1);
lcdHRetraceEnd += (lcdHRetraceEnd << 1);
lcdHTotal += (lcdHTotal << 1);
}
lcdHRetraceStart -=8;
lcdHRetraceEnd -=8;
} else {
lcdHTotal = mode->CrtcHTotal;
lcdHRetraceStart = mode->CrtcHSyncStart;
lcdHRetraceEnd = mode->CrtcHSyncEnd;
}
lcdHDisplay = cPtr->PanelSize.HDisplay;
if (pScrn->bitsPerPixel == 16) {
lcdHDisplay++;
lcdHDisplay <<= 1;
lcdHDisplay--;
} else if (pScrn->bitsPerPixel == 24) {
lcdHDisplay++;
lcdHDisplay += (lcdHDisplay << 1);
lcdHDisplay--;
}
lcdHTotal = (lcdHTotal >> 3) - 5;
lcdHDisplay = (lcdHDisplay >> 3) - 1;
lcdHRetraceStart = (lcdHRetraceStart >> 3);
lcdHRetraceEnd = (lcdHRetraceEnd >> 3);
CrtcHDisplay = ((mode->CrtcHDisplay >> 3) - 1);
if ((lcdHDisplay & 0x100) != (CrtcHDisplay & 0x100)) {
xf86ErrorF("This display configuration might cause problems !\n");
lcdHDisplay = 255;
}
ChipsNew->XR[0x17] = (((lcdHTotal) & 0x100) >> 8)
| ((lcdHDisplay & 0x100) >> 7)
| ((lcdHRetraceStart & 0x100) >> 6)
| (((lcdHRetraceEnd) & 0x20) >> 2);
ChipsNew->XR[0x19] = lcdHRetraceStart & 0xFF;
ChipsNew->XR[0x1A] = lcdHRetraceEnd & 0x1F;
ChipsNew->XR[0x1B] = lcdHTotal & 0xFF;
ChipsNew->XR[0x1C] = lcdHDisplay & 0xFF;
if (xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
ChipsNew->XR[0x21] = lcdHRetraceStart & 0xFF;
ChipsNew->XR[0x22] = lcdHRetraceEnd & 0x1F;
ChipsNew->XR[0x23] = lcdHTotal & 0xFF;
lcdVTotal = mode->CrtcVTotal - 2;
lcdVDisplay = cPtr->PanelSize.VDisplay - 1;
lcdVRetraceStart = mode->CrtcVSyncStart;
lcdVRetraceEnd = mode->CrtcVSyncEnd;
ChipsNew->XR[0x64] = lcdVTotal & 0xFF;
ChipsNew->XR[0x66] = lcdVRetraceStart & 0xFF;
ChipsNew->XR[0x67] = lcdVRetraceEnd & 0x0F;
ChipsNew->XR[0x68] = lcdVDisplay & 0xFF;
ChipsNew->XR[0x65] = ((lcdVTotal & 0x100) >> 8)
| ((lcdVDisplay & 0x100) >> 7)
| ((lcdVRetraceStart & 0x100) >> 6)
| ((lcdVRetraceStart & 0x400) >> 7)
| ((lcdVTotal & 0x400) >> 6)
| ((lcdVTotal & 0x200) >> 4)
| ((lcdVDisplay & 0x200) >> 3)
| ((lcdVRetraceStart & 0x200) >> 2);
tmp = ((cPtr->PanelType & ChipsDD) && !(ChipsNew->XR[0x6F] & 0x02))
? 1 : 0;
if (ChipsNew->XR[0x2C] < abs((cPtr->PanelSize.VTotal -
cPtr->PanelSize.VRetraceStart - tmp - 1) -
ChipsNew->XR[0x2C]))
ChipsNew->XR[0x2F] |= 0x80;
ChipsNew->XR[0x2C] = lcdVTotal - lcdVRetraceStart - tmp;
ChipsNew->XR[0x2D] = (HDisplay >> (3 - tmp)) & 0xFF;
ChipsNew->XR[0x2F] = (ChipsNew->XR[0x2F] & 0xDF)
| (((HSyncStart >> (3 - tmp)) & 0x100) >> 3);
}
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_SUSPEND_HACK, FALSE)) {
ChipsNew->XR[0x51] |= 0x40;
ChipsNew->XR[0x55] |= 0x01;
ChipsNew->XR[0x57] |= 0x01;
if (xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_STRETCH,
FALSE)) {
if (mode->CrtcHDisplay < 1489)
ChipsNew->XR[0x55] |= 0x02;
else if (pScrn->bitsPerPixel == 24)
ChipsNew->XR[0x56] = (lcdHDisplay - CrtcHDisplay) >> 1;
} else {
ChipsNew->XR[0x55] &= 0xFD;
ChipsNew->XR[0x56] = 0;
}
ChipsNew->XR[0x57] = 0x03;
if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_STRETCH,
FALSE)) {
ChipsNew->XR[0x55] |= 0x20;
ChipsNew->XR[0x57] |= 0x60;
tmp = (mode->CrtcVDisplay / (cPtr->PanelSize.VDisplay -
mode->CrtcVDisplay + 1));
if (tmp) {
if (cPtr->PanelSize.HDisplay
&& cPtr->PanelSize.VDisplay
&& (cPtr->PanelSize.HDisplay != mode->CrtcHDisplay)
&& (cPtr->PanelSize.VDisplay != mode->CrtcVDisplay)) {
if(cPtr->Accel.UseHWCursor)
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Disabling HW Cursor on stretched LCD\n");
cPtr->Flags &= ~ChipsHWCursor;
}
}
if (cPtr->Flags & ChipsHWCursor)
tmp = (tmp == 0 ? 1 : tmp);
ChipsNew->XR[0x5A] = tmp > 0x0F ? 0 : (unsigned char)tmp;
} else {
ChipsNew->XR[0x55] &= 0xDF;
ChipsNew->XR[0x57] &= 0x9F;
}
}
}
ChipsNew->XR[0x2B] = chipsVideoMode(pScrn->depth, (cPtr->PanelType & ChipsLCD) ?
min(HDisplay, cPtr->PanelSize.HDisplay) : HDisplay,cPtr->PanelSize.VDisplay);
#ifdef DEBUG
ErrorF("VESA Mode: %Xh\n", ChipsNew->XR[0x2B]);
#endif
if (cPtr->Flags & ChipsLinearSupport) {
ChipsNew->XR[0x0B] &= 0xFD;
ChipsNew->XR[0x0B] |= 0x10;
if (cPtr->Chipset == CHIPS_CT65535)
ChipsNew->XR[0x08] = (unsigned char)(cPtr->FbAddress >> 17);
else if (cPtr->Chipset > CHIPS_CT65535)
ChipsNew->XR[0x08] = (unsigned char)(cPtr->FbAddress >> 20);
else {
if (cPtr->Bus == ChipsISA)
ChipsNew->XR[0x04] &= ~0x40;
if (pScrn->videoRam > 512)
ChipsNew->XR[0x04] |= 0x40;
}
ChipsNew->XR[0x03] |= 0x08;
ChipsNew->XR[0x40] = 0x01;
}
ChipsNew->XR[0x52] |= 0x01;
ChipsNew->XR[0x0F] &= 0xEF;
ChipsNew->XR[0x02] |= 0x01;
ChipsNew->XR[0x02] &= 0xE3;
ChipsNew->XR[0x06] &= 0xF3;
if (cPtr->Bus == ChipsPCI)
ChipsNew->XR[0x03] |= 0x40;
if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
&& (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
if (mode->Flags & (V_PHSYNC | V_NHSYNC)) {
if (mode->Flags & V_PHSYNC) {
ChipsNew->XR[0x55] &= 0xBF;
} else {
ChipsNew->XR[0x55] |= 0x40;
}
}
if (mode->Flags & (V_PVSYNC | V_NVSYNC)) {
if (mode->Flags & V_PVSYNC) {
ChipsNew->XR[0x55] &= 0x7F;
} else {
ChipsNew->XR[0x55] |= 0x80;
}
}
}
if (pScrn->bitsPerPixel == 16) {
ChipsNew->XR[0x06] |= 0xC4;
ChipsNew->XR[0x0F] |= 0x10;
ChipsNew->XR[0x40] = 0x02;
if (pScrn->weight.green != 5)
ChipsNew->XR[0x06] |= 0x08;
} else if (pScrn->bitsPerPixel == 24) {
ChipsNew->XR[0x06] |= 0xC8;
ChipsNew->XR[0x0F] |= 0x10;
if (xf86ReturnOptValBool(cPtr->Options, OPTION_18_BIT_BUS, FALSE)) {
ChipsNew->XR[0x50] &= 0x7F;
} else {
ChipsNew->XR[0x50] |= 0x80;
}
}
if (!(cPtr->PanelType & ChipsLCD)) {
if (mode->Flags & V_INTERLACE){
ChipsNew->XR[0x28] |= 0x20;
tmp = ((((mode->CrtcHDisplay >> 3) - 1) >> 1)
- 6 * (pScrn->bitsPerPixel >= 8 ? bytesPerPixel : 1 ));
if(cPtr->Chipset < CHIPS_CT65535)
ChipsNew->XR[0x19] = tmp & 0xFF;
else
ChipsNew->XR[0x29] = tmp & 0xFF;
ChipsNew->XR[0x0F] &= ~0x40;
} else {
ChipsNew->XR[0x28] &= ~0x20;
ChipsNew->XR[0x0F] |= 0x40;
}
}
if (IS_STN(cPtr->PanelType)) {
ChipsNew->XR[0x50] &= ~0x03;
ChipsNew->XR[0x50] |= 0x01;
ChipsNew->XR[0x50] &= ~0x0C;
ChipsNew->XR[0x50] |= 0x08;
if (cPtr->Chipset == CHIPS_CT65548) {
ChipsNew->XR[0x03] |= 0x20;
ChipsNew->XR[0x04] |= 0x10;
}
}
switch (cPtr->Chipset) {
case CHIPS_CT65545:
ChipsNew->XR[0x03] |= 0x10;
break;
case CHIPS_CT65546:
ChipsNew->XR[0x05] |= 0x80;
break;
}
if (cPtr->PanelType & ChipsLCD)
ChipsNew->XR[0x51] |= 0x04;
else
ChipsNew->XR[0x51] &= ~0x04;
chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
return (TRUE);
}
static void
chipsRestore(ScrnInfoPtr pScrn, vgaRegPtr VgaReg, CHIPSRegPtr ChipsReg,
Bool restoreFonts)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char tmp = 0;
if (IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr, 0x0E, 0x00);
if (cPtr->Flags & ChipsDualChannelSupport) {
tmp = cPtr->readFR(cPtr, 0x01);
cPtr->writeFR(cPtr, 0x01, (tmp & 0xFC));
cPtr->writeFR(cPtr, 0x02, 0x00);
}
} else {
cPtr->writeXR(cPtr, 0x10, 0x00);
cPtr->writeXR(cPtr, 0x11, 0x00);
tmp = cPtr->readXR(cPtr, 0x0C) & ~0x50;
cPtr->writeXR(cPtr, 0x0C, tmp);
cPtr->writeXR(cPtr, 0x15, 0x00);
tmp = cPtr->readXR(cPtr, 0x14);
cPtr->writeXR(cPtr, 0x14, tmp & ~0x20);
}
chipsFixResume(pScrn);
if ((cPtr->SyncResetIgn) && (!(cPtr->Flags & ChipsDualChannelSupport))) {
while (((hwp->readST01(hwp)) & 0x08) == 0x08);
while (((hwp->readST01(hwp)) & 0x08) == 0x00);
hwp->writeSeq(hwp, 0x07, 0x00);
}
chipsClockLoad(pScrn, &ChipsReg->Clock);
VgaReg->MiscOutReg = inb(cPtr->PIOBase + 0x3CC);
chipsRestoreExtendedRegs(pScrn, ChipsReg);
#if 0
for (i=0; i<25; i++)
hwp->writeCrtc(hwp, i, VgaReg->CRTC[i]);
#endif
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtr->writeFR(cPtr, 0x01, ChipsReg->FR[0x01]);
cPtr->writeFR(cPtr, 0x02, ChipsReg->FR[0x02]);
vgaHWRestore(pScrn, VgaReg, VGA_SR_MODE |
(restoreFonts ? VGA_SR_FONTS : 0));
} else {
vgaHWRestore(pScrn, VgaReg, VGA_SR_MODE | VGA_SR_CMAP |
(restoreFonts ? VGA_SR_FONTS : 0));
}
if (IS_HiQV(cPtr)) {
chipsRestoreStretching(pScrn, (unsigned char)ChipsReg->FR[0x40],
(unsigned char)ChipsReg->FR[0x48]);
#if 0
chipsRestoreStretching(pScrn, (unsigned char)ChipsReg->FR[0x40],
(unsigned char)ChipsReg->FR[0x48]);
#endif
} else if (!IS_Wingine(cPtr))
chipsRestoreStretching(pScrn, (unsigned char)ChipsReg->XR[0x55],
(unsigned char)ChipsReg->XR[0x57]);
if (!cPtr->SyncResetIgn) {
if (!IS_HiQV(cPtr)) {
tmp = cPtr->readXR(cPtr, 0x0E);
cPtr->writeXR(cPtr, 0x0E, tmp & 0x7F);
}
hwp->writeSeq(hwp, 0x00, 0x01);
usleep(10000);
hwp->writeSeq(hwp, 0x00, 0x03);
if (!IS_HiQV(cPtr))
cPtr->writeXR(cPtr, 0x0E, tmp);
}
if (IS_HiQV(cPtr) && (ChipsReg->XR[0x09] & 0x1) == 0x1) {
tmp = hwp->readCrtc(hwp, 0x40);
hwp->writeCrtc(hwp, 0x40, tmp | 0x80);
}
chipsFixResume(pScrn);
#if 0
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtr->writeFR(cPtr, 0x01, ChipsReg->FR[0x01]);
cPtr->writeFR(cPtr, 0x02, ChipsReg->FR[0x02]);
}
#endif
}
static void
chipsRestoreExtendedRegs(ScrnInfoPtr pScrn, CHIPSRegPtr Regs)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
int i;
unsigned char tmp;
if (IS_HiQV(cPtr)) {
for (i = 0; i < 0x43; i++) {
if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
cPtr->writeXR(cPtr, i, Regs->XR[i]);
}
if ((cPtr->Flags & ChipsOverlay8plus16)
|| (cPtr->Flags & ChipsVideoSupport)) {
#ifdef SAR04
cPtr->writeXR(cPtr, 0x4E, 0x04);
if (cPtr->readXR(cPtr, 0x4F) != Regs->XR[0x4F])
cPtr->writeXR(cPtr, 0x4F, Regs->XR[0x4F]);
#endif
}
for (i = 0x50; i < 0xBF; i++) {
if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
cPtr->writeXR(cPtr, i, Regs->XR[i]);
}
tmp = cPtr->readXR(cPtr, 0xCE);
cPtr->writeXR(cPtr, 0xCE, tmp & 0x7F);
if ((cPtr->readXR(cPtr, 0xCC)) != Regs->XR[0xCC])
cPtr->writeXR(cPtr, 0xCC, Regs->XR[0xCC]);
if ((cPtr->readXR(cPtr, 0xCD)) != Regs->XR[0xCD])
cPtr->writeXR(cPtr, 0xCD, Regs->XR[0xCD]);
if ((cPtr->readXR(cPtr, 0xCE)) != Regs->XR[0xCE])
cPtr->writeXR(cPtr, 0xCE, Regs->XR[0xCE]);
for (i = 0xD0; i < 0xFF; i++) {
if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
cPtr->writeXR(cPtr, i, Regs->XR[i]);
}
for (i = 0; i < 0x80; i++) {
if ((i == 0x01) && (cPtr->Chipset == CHIPS_CT69030)) {
tmp = cPtr->readFR(cPtr, 0x01);
cPtr->writeFR(cPtr, 0x01, ((Regs->FR[0x01] & 0xF0) |
(tmp & ~0xF0)));
continue;
}
if ((i == 0x02) && (cPtr->Chipset == CHIPS_CT69030))
continue;
if ((i == 0x03) && (cPtr->Chipset != CHIPS_CT69030)) {
tmp = cPtr->readFR(cPtr, 0x03);
cPtr->writeFR(cPtr, 0x03, ((Regs->FR[0x03] & 0xC3) |
(tmp & ~0xC3)));
continue;
}
if ((i > 0x03) && (cPtr->Chipset != CHIPS_CT69030) &&
(cPtr->SecondCrtc == TRUE))
continue;
if ( (i == 0x40) || (i==0x48)) {
cPtr->writeFR(cPtr, i, Regs->FR[i] & 0xFE);
continue ;
}
if ((cPtr->readFR(cPtr, i)) != Regs->FR[i]) {
cPtr->writeFR(cPtr, i, Regs->FR[i]);
}
}
for (i = 0x02; i < 0x80; i++) {
if ( (i == 0x43) || (i == 0x44))
continue;
if ((cPtr->readMR(cPtr, i)) != Regs->MR[i])
cPtr->writeMR(cPtr, i, Regs->MR[i]);
}
for (i = 0x30; i < 0x80; i++) {
if ((hwp->readCrtc(hwp, i)) != Regs->CR[i])
hwp->writeCrtc(hwp, i, Regs->CR[i]);
}
} else {
for (i = 0; i < 0x30; i++) {
if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
cPtr->writeXR(cPtr, i, Regs->XR[i]);
}
cPtr->writeXR(cPtr, 0x15, 0x00);
for (i = 0x34; i < 0x54; i++) {
if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
cPtr->writeXR(cPtr, i, Regs->XR[i]);
}
tmp = cPtr->readXR(cPtr, 0x54);
cPtr->writeXR(cPtr, 0x54, ((Regs->XR[0x54] & 0xF3) | (tmp & ~0xF3)));
cPtr->writeXR(cPtr, 0x55, Regs->XR[0x55] & 0xFE);
cPtr->writeXR(cPtr, 0x56, Regs->XR[0x56]);
cPtr->writeXR(cPtr, 0x57, Regs->XR[0x57] & 0xFE);
for (i=0x58; i < 0x7D; i++) {
if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
cPtr->writeXR(cPtr, i, Regs->XR[i]);
}
}
#ifdef DEBUG
if (IS_HiQV(cPtr)) {
for (i = 0; i < 0xFF; i++) {
ErrorF("XR%X - %X : %X\n", i, Regs->XR[i],
cPtr->readXR(cPtr, i));
}
for (i = 0; i < 0x80; i++) {
ErrorF("FR%X - %X : %X\n", i, Regs->FR[i],
cPtr->readFR(cPtr, i));
}
} else {
for (i = 0; i < 0x80; i++) {
ErrorF("XR%X - %X : %X\n", i, Regs->XR[i],
cPtr->readXR(cPtr, i));
}
}
#endif
}
static void
chipsRestoreStretching(ScrnInfoPtr pScrn, unsigned char ctHorizontalStretch,
unsigned char ctVerticalStretch)
{
unsigned char tmp;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
if (IS_HiQV(cPtr)) {
tmp = cPtr->readFR(cPtr, 0x48);
cPtr->writeFR(cPtr, 0x48, (tmp & 0xFE) | (ctVerticalStretch & 0x01));
tmp = cPtr->readFR(cPtr, 0x40);
cPtr->writeFR(cPtr, 0x40, (tmp & 0xFE) | (ctHorizontalStretch & 0x01));
} else {
tmp = cPtr->readXR(cPtr, 0x55);
cPtr->writeXR(cPtr, 0x55, (tmp & 0xFE) | (ctHorizontalStretch & 0x01));
tmp = cPtr->readXR(cPtr, 0x57);
cPtr->writeXR(cPtr, 0x57, (tmp & 0xFE) | (ctVerticalStretch & 0x01));
}
usleep(20000);
}
static int
chipsVideoMode(int depth, int displayHSize,
int displayVSize)
{
int videoMode = 0;
switch (depth) {
case 1:
case 4:
videoMode = 0x20;
break;
case 8:
videoMode = 0x30;
break;
case 15:
videoMode = 0x40;
break;
case 16:
videoMode = 0x41;
break;
default:
videoMode = 0x50;
break;
}
switch (displayHSize) {
case 800:
videoMode |= 0x02;
break;
case 1024:
videoMode |= 0x04;
if(displayVSize < 768)
videoMode |= 0x02;
break;
case 1152:
videoMode |= 0x07;
break;
case 1280:
videoMode |= 0x08;
break;
case 1600:
videoMode |= 0x0C;
break;
}
return videoMode;
}
static Bool
chipsMapMem(ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSEntPtr cPtrEnt;
if (cPtr->Flags & ChipsLinearSupport) {
if (cPtr->UseMMIO) {
if (IS_HiQV(cPtr)) {
if (cPtr->Bus == ChipsPCI)
cPtr->MMIOBase = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT,cPtr->PciTag, cPtr->IOAddress,
0x20000L);
else
cPtr->MMIOBase = xf86MapVidMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT, cPtr->IOAddress, 0x20000L);
} else {
if (cPtr->Bus == ChipsPCI)
cPtr->MMIOBase = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT, cPtr->PciTag, cPtr->IOAddress,
0x10000L);
else
cPtr->MMIOBase = xf86MapVidMem(pScrn->scrnIndex,
VIDMEM_MMIO_32BIT, cPtr->IOAddress, 0x10000L);
}
if (cPtr->MMIOBase == NULL)
return FALSE;
}
if (cPtr->FbMapSize) {
unsigned long Addr = (unsigned long)cPtr->FbAddress;
unsigned int Map = cPtr->FbMapSize;
if ((cPtr->Flags & ChipsDualChannelSupport) &&
(xf86IsEntityShared(pScrn->entityList[0]))) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
if(cPtr->SecondCrtc == FALSE) {
Addr = cPtrEnt->masterFbAddress;
Map = cPtrEnt->masterFbMapSize;
} else {
Addr = cPtrEnt->slaveFbAddress;
Map = cPtrEnt->slaveFbMapSize;
}
}
if (cPtr->Bus == ChipsPCI)
cPtr->FbBase = xf86MapPciMem(pScrn->scrnIndex,VIDMEM_FRAMEBUFFER,
cPtr->PciTag, Addr, Map);
else
cPtr->FbBase = xf86MapVidMem(pScrn->scrnIndex,VIDMEM_FRAMEBUFFER,
Addr, Map);
if (cPtr->FbBase == NULL)
return FALSE;
}
if (cPtr->Flags & ChipsFullMMIOSupport) {
cPtr->MMIOBaseVGA = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO,cPtr->PciTag,
cPtr->IOAddress, 0x2000L);
if (cPtr->Flags & ChipsDualChannelSupport)
cPtr->MMIOBasePipeB = xf86MapPciMem(pScrn->scrnIndex,
VIDMEM_MMIO,cPtr->PciTag,
cPtr->IOAddress + 0x800000, 0x2000L);
cPtr->MMIOBasePipeA = cPtr->MMIOBaseVGA;
}
} else {
cPtr->FbBase = hwp->Base;
}
return TRUE;
}
static Bool
chipsUnmapMem(ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
if (cPtr->Flags & ChipsLinearSupport) {
if (IS_HiQV(cPtr)) {
if (cPtr->MMIOBase)
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBase,
0x20000);
if (cPtr->MMIOBasePipeB)
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBasePipeB,
0x20000);
cPtr->MMIOBasePipeB = NULL;
} else {
if (cPtr->MMIOBase)
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBase,
0x10000);
}
cPtr->MMIOBase = NULL;
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->FbBase,
cPtr->FbMapSize);
}
cPtr->FbBase = NULL;
return TRUE;
}
static void
chipsProtect(ScrnInfoPtr pScrn, Bool on)
{
vgaHWProtect(pScrn, on);
}
static void
chipsBlankScreen(ScrnInfoPtr pScrn, Bool unblank)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
vgaHWPtr hwp = VGAHWPTR(pScrn);
unsigned char scrn;
CHIPSEntPtr cPtrEnt;
if (cPtr->UseDualChannel) {
cPtrEnt = xf86GetEntityPrivate(pScrn->entityList[0],
CHIPSEntityIndex)->ptr;
DUALREOPEN;
}
if (!IS_HiQV(cPtr))
cPtr->writeXR(cPtr, 0x15, 0x00);
scrn = hwp->readSeq(hwp, 0x01);
if (unblank) {
scrn &= 0xDF;
} else {
scrn |= 0x20;
}
if (!cPtr->SyncResetIgn) {
hwp->writeSeq(hwp, 0x00, 0x01);
}
hwp->writeSeq(hwp, 0x01, scrn);
if (!cPtr->SyncResetIgn) {
hwp->writeSeq(hwp, 0x00, 0x03);
}
if ((cPtr->UseDualChannel) &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
if (!IS_HiQV(cPtr))
cPtr->writeXR(cPtr, 0x15, 0x00);
scrn = hwp->readSeq(hwp, 0x01);
if (unblank) {
scrn &= 0xDF;
} else {
scrn |= 0x20;
}
if (!cPtr->SyncResetIgn) {
hwp->writeSeq(hwp, 0x00, 0x01);
}
hwp->writeSeq(hwp, 0x01, scrn);
if (!cPtr->SyncResetIgn) {
hwp->writeSeq(hwp, 0x00, 0x03);
}
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
}
}
static void
chipsLock(ScrnInfoPtr pScrn)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char tmp;
vgaHWLock(hwp);
if (!IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr, 0x15, cPtr->SuspendHack.xr15);
tmp = cPtr->readXR(cPtr, 0x02);
cPtr->writeXR(cPtr, 0x02, (tmp & ~0x18) | cPtr->SuspendHack.xr02);
tmp = cPtr->readXR(cPtr, 0x14);
cPtr->writeXR(cPtr, 0x14, (tmp & ~0x20) | cPtr->SuspendHack.xr14);
if (cPtr->Chipset > CHIPS_CT65540) {
tmp = cPtr->readXR(cPtr, 0x03);
cPtr->writeXR(cPtr, 0x03, (tmp & ~0x0A) | cPtr->SuspendHack.xr03);
}
}
}
static void
chipsUnlock(ScrnInfoPtr pScrn)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
CHIPSPtr cPtr = CHIPSPTR(pScrn);
unsigned char tmp;
if (!IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr, 0x15, 0x00);
tmp = cPtr->readXR(cPtr, 0x02);
cPtr->writeXR(cPtr, 0x02, (tmp & ~0x18));
tmp = cPtr->readXR(cPtr, 0x14);
cPtr->writeXR(cPtr, 0x14, (tmp & ~0x20));
if (cPtr->Chipset > CHIPS_CT65540) {
cPtr->writeXR(cPtr, 0x03, cPtr->SuspendHack.xr03 | 0x0A);
}
}
vgaHWUnlock(hwp);
}
static void
chipsHWCursorOn(CHIPSPtr cPtr, ScrnInfoPtr pScrn)
{
if (cPtr->HWCursorShown) {
if (IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr, 0xA0, cPtr->HWCursorContents & 0xFF);
if (cPtr->UseDualChannel &&
(! xf86IsEntityShared(pScrn->entityList[0]))) {
unsigned int IOSS, MSS;
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
IOSS_PIPE_B));
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &
MSS_MASK) | MSS_PIPE_B));
cPtr->writeXR(cPtr, 0xA0, cPtr->HWCursorContents & 0xFF);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), MSS);
}
} else {
HW_DEBUG(0x8);
if (cPtr->UseMMIO) {
MMIOmeml(DR(0x8)) = cPtr->HWCursorContents;
} else {
outl(cPtr->PIOBase + DR(0x8), cPtr->HWCursorContents);
}
}
}
}
static void
chipsHWCursorOff(CHIPSPtr cPtr, ScrnInfoPtr pScrn)
{
if (cPtr->HWCursorShown) {
if (IS_HiQV(cPtr)) {
cPtr->HWCursorContents = cPtr->readXR(cPtr, 0xA0);
cPtr->writeXR(cPtr, 0xA0, cPtr->HWCursorContents & 0xF8);
} else {
HW_DEBUG(0x8);
if (cPtr->UseMMIO) {
cPtr->HWCursorContents = MMIOmeml(DR(0x8));
MMIOmeml(DR(0x8)) = cPtr->HWCursorContents & 0xFFFE;
} else {
cPtr->HWCursorContents = inl(cPtr->PIOBase + DR(0x8));
outw(cPtr->PIOBase + DR(0x8), cPtr->HWCursorContents & 0xFFFE);
}
}
}
}
void
chipsFixResume(ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
vgaHWPtr hwp = VGAHWPTR(pScrn);
unsigned char tmp;
if (!IS_HiQV(cPtr))
cPtr->writeXR(cPtr, 0x15, 0x00);
tmp = hwp->readMiscOut(hwp);
hwp->writeMiscOut(hwp, (tmp & 0xFE) | cPtr->SuspendHack.vgaIOBaseFlag);
tmp = hwp->readCrtc(hwp, 0x11);
hwp->writeCrtc(hwp, 0x11, (tmp & 0x7F));
}
static char
chipsTestDACComp(ScrnInfoPtr pScrn, unsigned char a, unsigned char b,
unsigned char c)
{
vgaHWPtr hwp = VGAHWPTR(pScrn);
unsigned char type;
hwp->writeDacWriteAddr(hwp, 0x00);
while ((hwp->readST01(hwp)) & 0x08){};
while (!(hwp->readST01(hwp)) & 0x08){};
hwp->writeDacData(hwp, a);
hwp->writeDacData(hwp, b);
hwp->writeDacData(hwp, c);
while (!(hwp->readST01(hwp)) & 0x01){};
while ((hwp->readST01(hwp)) & 0x01){};
type = hwp->readST00(hwp);
return (type & 0x10);
}
static int
chipsProbeMonitor(ScrnInfoPtr pScrn)
{
CHIPSPtr cPtr = CHIPSPTR(pScrn);
vgaHWPtr hwp = VGAHWPTR(pScrn);
unsigned char dacmask;
unsigned char dacdata[3];
unsigned char xr1, xr2;
int type = 2;
unsigned char IOSS=0, MSS=0, tmpfr02=0, tmpfr01a=0, tmpfr01b=0;
if (cPtr->Flags & ChipsDualChannelSupport) {
IOSS = cPtr->readIOSS(cPtr);
MSS = cPtr->readMSS(cPtr);
tmpfr02 = cPtr->readFR(cPtr,0x02);
cPtr->writeFR(cPtr, 0x02, (tmpfr02 & 0xCF));
usleep(1000);
cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_A));
cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_A));
tmpfr01a = cPtr->readFR(cPtr,0x01);
if ((tmpfr01a & 0x3) != 0x01)
cPtr->writeFR(cPtr, 0x01, ((tmpfr01a & 0xFC) | 0x1));
cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_B));
tmpfr01b = cPtr->readFR(cPtr,0x01);
if ((tmpfr01b & 0x3) != 0x01)
cPtr->writeFR(cPtr, 0x01, ((tmpfr01b & 0xFC) | 0x1));
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
cPtr->writeFR(cPtr, 0x02, (tmpfr02 & 0xCF) | 0x10);
}
dacmask = hwp->readDacMask(hwp);
hwp->writeDacMask(hwp, 0x00);
hwp->writeDacReadAddr(hwp, 0x00);
dacdata[0]=hwp->readDacData(hwp);
dacdata[1]=hwp->readDacData(hwp);
dacdata[2]=hwp->readDacData(hwp);
if (!IS_HiQV(cPtr)) {
xr1 = cPtr->readXR(cPtr, 0x06);
xr2 = cPtr->readXR(cPtr, 0x1F);
cPtr->writeXR(cPtr, 0x06, xr1 & 0xF1);
cPtr->writeXR(cPtr, 0x1F, xr2 & 0x7F);
} else {
xr1 = cPtr->readXR(cPtr, 0x81);
xr2 = cPtr->readXR(cPtr, 0xD0);
cPtr->writeXR(cPtr, 0x81,(xr1 & 0xF0));
cPtr->writeXR(cPtr, 0xD0,(xr2 | 0x03));
}
if (chipsTestDACComp(pScrn, 0x12,0x12,0x12)) {
if (chipsTestDACComp(pScrn,0x14,0x14,0x14))
if (!chipsTestDACComp(pScrn,0x2D,0x14,0x14))
if (!chipsTestDACComp(pScrn,0x14,0x2D,0x14))
if (!chipsTestDACComp(pScrn,0x14,0x14,0x2D))
if (!chipsTestDACComp(pScrn,0x2D,0x2D,0x2D))
type = 0;
} else {
if (chipsTestDACComp(pScrn,0x04,0x12,0x04))
if (!chipsTestDACComp(pScrn,0x1E,0x12,0x04))
if (!chipsTestDACComp(pScrn,0x04,0x2D,0x04))
if (!chipsTestDACComp(pScrn,0x1E,0x16,0x15))
if (chipsTestDACComp(pScrn,0x00,0x00,0x00))
type = 1;
}
hwp->writeDacWriteAddr(hwp, 0x00);
hwp->writeDacData(hwp, dacdata[0]);
hwp->writeDacData(hwp, dacdata[1]);
hwp->writeDacData(hwp, dacdata[2]);
hwp->writeDacMask(hwp, dacmask);
if (!IS_HiQV(cPtr)) {
cPtr->writeXR(cPtr,0x06,xr1);
cPtr->writeXR(cPtr,0x1F,xr2);
} else {
cPtr->writeXR(cPtr,0x81,xr1);
cPtr->writeXR(cPtr,0xD0,xr2);
}
if (cPtr->Flags & ChipsDualChannelSupport) {
cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_A));
cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_A));
cPtr->writeFR(cPtr, 0x01, tmpfr01a);
cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_B));
cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_B));
cPtr->writeFR(cPtr, 0x01, tmpfr01b);
usleep(1000);
cPtr->writeIOSS(cPtr, IOSS);
cPtr->writeMSS(cPtr, hwp, MSS);
cPtr->writeFR(cPtr, 0x02, tmpfr02);
}
return type;
}
static int
chipsSetMonitor(ScrnInfoPtr pScrn)
{
int tmp= chipsProbeMonitor(pScrn);
switch (tmp) {
case 0:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Color monitor detected\n");
break;
case 1:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Monochrome monitor detected\n");
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "No monitor detected\n");
}
return (tmp);
}
static void
chipsSetPanelType(CHIPSPtr cPtr)
{
CARD8 tmp;
if (IS_HiQV(cPtr)) {
if (cPtr->Chipset == CHIPS_CT69030) {
tmp = cPtr->readFR(cPtr, 0x00);
if (tmp & 0x20) {
tmp = cPtr->readFR(cPtr, 0x02);
if (tmp & 0x10)
cPtr->PanelType |= ChipsCRT;
if (tmp & 0x20)
cPtr->PanelType |= ChipsLCD | ChipsLCDProbed;
} else {
cPtr->PanelType |= ChipsCRT;
}
} else {
tmp = cPtr->readFR(cPtr, 0x01);
if ((tmp & 0x03) == 0x02) {
cPtr->PanelType |= ChipsLCD | ChipsLCDProbed;
}
tmp = cPtr->readXR(cPtr,0xD0);
if (tmp & 0x01) {
cPtr->PanelType |= ChipsCRT;
}
}
} else {
tmp = cPtr->readXR(cPtr, 0x51);
if (tmp & 0x04) {
cPtr->PanelType |= ChipsLCD | ChipsLCDProbed;
}
if ((cPtr->readXR(cPtr, 0x06)) & 0x02) {
cPtr->PanelType |= ChipsCRT;
}
}
}
static void
chipsBlockHandler (
int i,
pointer blockData,
pointer pTimeout,
pointer pReadmask
){
ScreenPtr pScreen = screenInfo.screens[i];
ScrnInfoPtr pScrn = xf86Screens[i];
CHIPSPtr cPtr = CHIPSPTR(pScrn);
pScreen->BlockHandler = cPtr->BlockHandler;
(*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
pScreen->BlockHandler = chipsBlockHandler;
if(cPtr->VideoTimerCallback) {
UpdateCurrentTime();
(*cPtr->VideoTimerCallback)(pScrn, currentTime.milliseconds);
}
}