#define DEBUG_TYPE "machine-sink"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
STATISTIC(NumSunk, "Number of machine instructions sunk");
namespace {
class MachineSinking : public MachineFunctionPass {
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
MachineRegisterInfo *RegInfo; MachineDominatorTree *DT; MachineLoopInfo *LI;
AliasAnalysis *AA;
BitVector AllocatableSet;
public:
static char ID; MachineSinking() : MachineFunctionPass(&ID) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
AU.addRequired<AliasAnalysis>();
AU.addRequired<MachineDominatorTree>();
AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineDominatorTree>();
AU.addPreserved<MachineLoopInfo>();
}
private:
bool ProcessBlock(MachineBasicBlock &MBB);
bool SinkInstruction(MachineInstr *MI, bool &SawStore);
bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const;
};
}
char MachineSinking::ID = 0;
static RegisterPass<MachineSinking>
X("machine-sink", "Machine code sinking");
FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); }
bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
MachineBasicBlock *MBB) const {
assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
"Only makes sense for vregs");
for (MachineRegisterInfo::use_nodbg_iterator I =
RegInfo->use_nodbg_begin(Reg),
E = RegInfo->use_nodbg_end(); I != E; ++I) {
MachineInstr *UseInst = &*I;
MachineBasicBlock *UseBlock = UseInst->getParent();
if (UseInst->isPHI()) {
UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB();
}
if (!DT->dominates(MBB, UseBlock))
return false;
}
return true;
}
bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "******** Machine Sinking ********\n");
const TargetMachine &TM = MF.getTarget();
TII = TM.getInstrInfo();
TRI = TM.getRegisterInfo();
RegInfo = &MF.getRegInfo();
DT = &getAnalysis<MachineDominatorTree>();
LI = &getAnalysis<MachineLoopInfo>();
AA = &getAnalysis<AliasAnalysis>();
AllocatableSet = TRI->getAllocatableSet(MF);
bool EverMadeChange = false;
while (1) {
bool MadeChange = false;
for (MachineFunction::iterator I = MF.begin(), E = MF.end();
I != E; ++I)
MadeChange |= ProcessBlock(*I);
if (!MadeChange) break;
EverMadeChange = true;
}
return EverMadeChange;
}
bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
if (MBB.succ_size() <= 1 || MBB.empty()) return false;
if (!DT->isReachableFromEntry(&MBB)) return false;
bool MadeChange = false;
MachineBasicBlock::iterator I = MBB.end();
--I;
bool ProcessedBegin, SawStore = false;
do {
MachineInstr *MI = I;
ProcessedBegin = I == MBB.begin();
if (!ProcessedBegin)
--I;
if (MI->isDebugValue())
continue;
if (SinkInstruction(MI, SawStore))
++NumSunk, MadeChange = true;
} while (!ProcessedBegin);
return MadeChange;
}
bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
if (!MI->isSafeToMove(TII, AA, SawStore))
return false;
MachineBasicBlock *ParentBlock = MI->getParent();
MachineBasicBlock *SuccToSinkTo = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
if (MO.isUse()) {
if (!RegInfo->def_empty(Reg))
return false;
if (AllocatableSet.test(Reg))
return false;
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
if (!RegInfo->def_empty(AliasReg))
return false;
if (AllocatableSet.test(AliasReg))
return false;
}
} else if (!MO.isDead()) {
return false;
}
} else {
if (MO.isUse()) continue;
if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg)))
return false;
if (SuccToSinkTo) {
if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo))
return false;
continue;
}
for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(),
E = ParentBlock->succ_end(); SI != E; ++SI) {
if (AllUsesDominatedByBlock(Reg, *SI)) {
SuccToSinkTo = *SI;
break;
}
}
if (SuccToSinkTo == 0)
return false;
}
}
if (SuccToSinkTo == 0)
return false;
if (SuccToSinkTo->isLandingPad())
return false;
if (MI->getParent() == SuccToSinkTo)
return false;
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I);
if (!MO.isReg()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
if (SuccToSinkTo->isLiveIn(Reg))
return false;
}
DEBUG(dbgs() << "Sink instr " << *MI);
DEBUG(dbgs() << "to block " << *SuccToSinkTo);
if (SuccToSinkTo->pred_size() > 1) {
bool store = true;
if (!MI->isSafeToMove(TII, AA, store)) {
DEBUG(dbgs() << " *** PUNTING: Wont sink load along critical edge.\n");
return false;
}
if (!DT->dominates(ParentBlock, SuccToSinkTo)) {
DEBUG(dbgs() << " *** PUNTING: Critical edge found\n");
return false;
}
if (LI->isLoopHeader(SuccToSinkTo)) {
DEBUG(dbgs() << " *** PUNTING: Loop header found\n");
return false;
}
DEBUG(dbgs() << "Sinking along critical edge.\n");
}
MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin();
while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
++InsertPos;
SuccToSinkTo->splice(InsertPos, ParentBlock, MI,
++MachineBasicBlock::iterator(MI));
return true;
}