#define DEBUG_TYPE "regalloc"
#include "llvm/BasicBlock.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
using namespace llvm;
STATISTIC(NumStores, "Number of stores added");
STATISTIC(NumLoads , "Number of loads added");
static RegisterRegAlloc
localRegAlloc("local", "local register allocator",
createLocalRegisterAllocator);
namespace {
class RALocal : public MachineFunctionPass {
public:
static char ID;
RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
private:
const TargetMachine *TM;
MachineFunction *MF;
const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
return Virt2PhysRegMap[VirtReg];
}
std::vector<int> PhysRegsUsed;
std::vector<unsigned> PhysRegsUseOrder;
IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
Virt2LastUseMap;
std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
return Virt2LastUseMap[Reg];
}
BitVector VirtRegModified;
BitVector UsedInMultipleBlocks;
void markVirtRegModified(unsigned Reg, bool Val = true) {
assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
Reg -= TargetRegisterInfo::FirstVirtualRegister;
if (Val)
VirtRegModified.set(Reg);
else
VirtRegModified.reset(Reg);
}
bool isVirtRegModified(unsigned Reg) const {
assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
assert(Reg - TargetRegisterInfo::FirstVirtualRegister <
VirtRegModified.size() && "Illegal virtual register!");
return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
}
void AddToPhysRegsUseOrder(unsigned Reg) {
std::vector<unsigned>::iterator It =
std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
if (It != PhysRegsUseOrder.end())
PhysRegsUseOrder.erase(It);
PhysRegsUseOrder.push_back(Reg);
}
void MarkPhysRegRecentlyUsed(unsigned Reg) {
if (PhysRegsUseOrder.empty() ||
PhysRegsUseOrder.back() == Reg) return;
for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) {
unsigned RegMatch = PhysRegsUseOrder[i-1]; if (!areRegsEqual(Reg, RegMatch)) continue;
PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
PhysRegsUseOrder.push_back(RegMatch);
if (RegMatch == Reg)
return; }
}
public:
virtual const char *getPassName() const {
return "Local Register Allocator";
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequiredID(PHIEliminationID);
AU.addRequiredID(TwoAddressInstructionPassID);
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
bool runOnMachineFunction(MachineFunction &Fn);
void AllocateBasicBlock(MachineBasicBlock &MBB);
bool areRegsEqual(unsigned R1, unsigned R2) const {
if (R1 == R2) return true;
for (const unsigned *AliasSet = TRI->getAliasSet(R2);
*AliasSet; ++AliasSet) {
if (*AliasSet == R1) return true;
}
return false;
}
int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
void removePhysReg(unsigned PhysReg);
void storeVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg, bool isKill);
void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned VirtReg, unsigned PhysReg);
void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
unsigned PhysReg, bool OnlyVirtRegs = false);
void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
bool isPhysRegAvailable(unsigned PhysReg) const;
unsigned getFreeReg(const TargetRegisterClass *RC);
unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned VirtReg, bool NoFree = false);
MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum, SmallSet<unsigned, 4> &RRegs,
unsigned PhysReg);
void ComputeLocalLiveness(MachineBasicBlock& MBB);
void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg);
};
char RALocal::ID = 0;
}
int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
int SS = StackSlotForVirtReg[VirtReg];
if (SS != -1)
return SS;
int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
RC->getAlignment());
StackSlotForVirtReg[VirtReg] = FrameIdx;
return FrameIdx;
}
void RALocal::removePhysReg(unsigned PhysReg) {
PhysRegsUsed[PhysReg] = -1;
std::vector<unsigned>::iterator It =
std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
if (It != PhysRegsUseOrder.end())
PhysRegsUseOrder.erase(It);
}
void RALocal::storeVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg,
bool isKill) {
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(dbgs() << " to stack slot #" << FrameIndex);
TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
++NumStores; }
void RALocal::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond"
" the intended one.");
DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
<< " containing %reg" << VirtReg);
if (!isVirtRegModified(VirtReg)) {
DEBUG(dbgs() << " which has not been modified, so no store necessary!");
std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
if (LastUse.first)
LastUse.first->getOperand(LastUse.second).setIsKill();
} else {
bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
storeVirtReg(MBB, I, VirtReg, PhysReg, isKill);
}
getVirt2PhysRegMapSlot(VirtReg) = 0;
DEBUG(dbgs() << '\n');
removePhysReg(PhysReg);
}
void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
unsigned PhysReg, bool OnlyVirtRegs) {
if (PhysRegsUsed[PhysReg] != -1) { assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
return;
}
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] == -1 || PhysRegsUsed[*AliasSet] == -2) continue;
if (PhysRegsUsed[*AliasSet])
spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
}
}
void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
PhysRegsUsed[PhysReg] = VirtReg;
getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
AddToPhysRegsUseOrder(PhysReg); }
bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
if (PhysRegsUsed[PhysReg] != -1) return false;
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
*AliasSet; ++AliasSet)
if (PhysRegsUsed[*AliasSet] >= 0) return false; return true;
}
unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
for (; RI != RE; ++RI)
if (isPhysRegAvailable(*RI)) { assert(*RI != 0 && "Cannot use register!");
return *RI; }
return 0;
}
unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
unsigned VirtReg, bool NoFree) {
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
if (PhysReg != 0) {
assignVirtToPhysReg(VirtReg, PhysReg);
return PhysReg;
}
assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
for (unsigned i = 0; PhysReg == 0; ++i) {
assert(i != PhysRegsUseOrder.size() &&
"Couldn't find a register of the appropriate class!");
unsigned R = PhysRegsUseOrder[i];
assert(PhysRegsUsed[R] != -1 &&
"PhysReg in PhysRegsUseOrder, but is not allocated?");
if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
if (RC->contains(R)) {
PhysReg = R;
break;
}
for (const unsigned *AliasIt = TRI->getAliasSet(R);
*AliasIt; ++AliasIt) {
if (!RC->contains(*AliasIt)) continue;
if (PhysRegsUsed[*AliasIt] == 0) continue;
if (PhysRegsUsed[*AliasIt] == -2) continue;
PhysReg = *AliasIt; break;
}
}
}
assert(PhysReg && "Physical register not assigned!?!?");
spillPhysReg(MBB, I, PhysReg);
assignVirtToPhysReg(VirtReg, PhysReg);
return PhysReg;
}
MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum,
SmallSet<unsigned, 4> &ReloadedRegs,
unsigned PhysReg) {
unsigned VirtReg = MI->getOperand(OpNum).getReg();
if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
MI->getOperand(OpNum).setReg(PR); if (!MI->isDebugValue()) {
MarkPhysRegRecentlyUsed(PR); getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
}
return MI;
}
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) ||
!isPhysRegAvailable(PhysReg))
PhysReg = getFreeReg(RC);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
if (PhysReg) { assignVirtToPhysReg(VirtReg, PhysReg);
} else { PhysReg = getReg(MBB, MI, VirtReg, true);
}
markVirtRegModified(VirtReg, false);
DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
<< TRI->getName(PhysReg) << "\n");
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads;
MF->getRegInfo().setPhysRegUsed(PhysReg);
MI->getOperand(OpNum).setReg(PhysReg); getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
if (!ReloadedRegs.insert(PhysReg)) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Ran out of registers during register allocation!";
if (MI->isInlineAsm()) {
Msg << "\nPlease check your inline asm statement for invalid "
<< "constraints:\n";
MI->print(Msg, TM);
}
llvm_report_error(Msg.str());
}
for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
*SubRegs; ++SubRegs) {
if (ReloadedRegs.insert(*SubRegs)) continue;
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Ran out of registers during register allocation!";
if (MI->isInlineAsm()) {
Msg << "\nPlease check your inline asm statement for invalid "
<< "constraints:\n";
MI->print(Msg, TM);
}
llvm_report_error(Msg.str());
}
return MI;
}
static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
MO.isDef() && !MO.isDead())
return true;
}
return false;
}
static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
!MO.isDef() && MO.isKill())
return true;
}
return false;
}
static bool precedes(MachineBasicBlock::iterator A,
MachineBasicBlock::iterator B) {
if (A == B)
return false;
MachineBasicBlock::iterator I = A->getParent()->begin();
while (I != A->getParent()->end()) {
if (I == A)
return true;
else if (I == B)
return false;
++I;
}
return false;
}
void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
if (I->isDebugValue())
continue;
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
if (!MO.isReg() || !MO.getReg() || !MO.isUse())
continue;
LastUseDef[MO.getReg()] = std::make_pair(I, i);
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
const unsigned *Aliases = TRI->getAliasSet(MO.getReg());
if (Aliases == 0)
continue;
while (*Aliases) {
DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
alias = LastUseDef.find(*Aliases);
if (alias != LastUseDef.end() && alias->second.first != I)
LastUseDef[*Aliases] = std::make_pair(I, i);
++Aliases;
}
}
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
if (!MO.isReg() || !MO.getReg() || !MO.isDef()) continue;
DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
last = LastUseDef.find(MO.getReg());
if (last != LastUseDef.end()) {
if (last->second.first == I &&
I->isRegTiedToUseOperand(i))
continue;
MachineOperand &lastUD =
last->second.first->getOperand(last->second.second);
if (lastUD.isDef())
lastUD.setIsDead(true);
else
lastUD.setIsKill(true);
}
LastUseDef[MO.getReg()] = std::make_pair(I, i);
}
}
MachineBasicBlock::iterator Ret = MBB.getFirstTerminator();
bool BBEndsInReturn = (Ret != MBB.end() && Ret->getDesc().isReturn());
if (BBEndsInReturn)
for (MachineRegisterInfo::liveout_iterator
I = MF->getRegInfo().liveout_begin(),
E = MF->getRegInfo().liveout_end(); I != E; ++I)
if (!Ret->readsRegister(*I)) {
Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
}
for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
MachineInstr *MI = I->second.first;
unsigned idx = I->second.second;
MachineOperand &MO = MI->getOperand(idx);
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
bool usedOutsideBlock = isPhysReg ? false :
UsedInMultipleBlocks.test(MO.getReg() -
TargetRegisterInfo::FirstVirtualRegister);
if (!isPhysReg && (!usedOutsideBlock || BBEndsInReturn)) {
bool UsedByDebugValueOnly = false;
for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
UE = MRI.reg_end(); UI != UE; ++UI) {
if (UI->getParent() == &MBB &&
!(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI)))
continue;
if (UI->isDebugValue()) {
UsedByDebugValueOnly = true;
continue;
}
UsedInMultipleBlocks.set(MO.getReg() -
TargetRegisterInfo::FirstVirtualRegister);
usedOutsideBlock = true;
UsedByDebugValueOnly = false;
break;
}
if (UsedByDebugValueOnly)
for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
UE = MRI.reg_end(); UI != UE; ++UI)
if (UI->isDebugValue() &&
(UI->getParent() != &MBB ||
(MO.isDef() && precedes(&*UI, MI))))
UI.getOperand().setReg(0U);
}
if (isPhysReg || !usedOutsideBlock || BBEndsInReturn)
if (MO.isUse()) {
if (!MI->isRegTiedToDefOperand(idx))
MO.setIsKill(true);
} else {
MO.setIsDead(true);
}
}
}
void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
MachineBasicBlock::iterator MII = MBB.begin();
DEBUG({
const BasicBlock *LBB = MBB.getBasicBlock();
if (LBB)
dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName();
});
for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
E = MBB.livein_end(); I != E; ++I) {
unsigned Reg = *I;
MF->getRegInfo().setPhysRegUsed(Reg);
PhysRegsUsed[Reg] = 0; AddToPhysRegsUseOrder(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
*SubRegs; ++SubRegs) {
if (PhysRegsUsed[*SubRegs] == -2) continue;
AddToPhysRegsUseOrder(*SubRegs);
PhysRegsUsed[*SubRegs] = 0; MF->getRegInfo().setPhysRegUsed(*SubRegs);
}
}
ComputeLocalLiveness(MBB);
while (MII != MBB.end()) {
MachineInstr *MI = MII++;
const TargetInstrDesc &TID = MI->getDesc();
DEBUG({
dbgs() << "\nStarting RegAlloc of: " << *MI;
dbgs() << " Regs have values: ";
for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
if (PhysRegsUsed[i] && isVirtRegModified(PhysRegsUsed[i]))
dbgs() << "*";
dbgs() << "[" << TRI->getName(i)
<< ",%reg" << PhysRegsUsed[i] << "] ";
}
dbgs() << '\n';
});
unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
unsigned SrcCopyPhysReg = 0U;
bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
SrcCopySubReg, DstCopySubReg);
if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
if (TID.ImplicitUses) {
for (const unsigned *ImplicitUses = TID.ImplicitUses;
*ImplicitUses; ++ImplicitUses)
MarkPhysRegRecentlyUsed(*ImplicitUses);
}
SmallVector<unsigned, 8> Kills;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isKill()) continue;
if (!MO.isImplicit())
Kills.push_back(MO.getReg());
else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
Kills.push_back(MO.getReg());
}
if (MI->isInlineAsm()) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber() ||
!MO.getReg())
continue;
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
DestPhysReg = getReg(MBB, MI, DestVirtReg);
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
markVirtRegModified(DestVirtReg);
getVirtRegLastUse(DestVirtReg) =
std::make_pair((MachineInstr*)0, 0);
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
<< " to %reg" << DestVirtReg << "\n");
MO.setReg(DestPhysReg); } else {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
MF->getRegInfo().setPhysRegUsed(Reg);
spillPhysReg(MBB, MI, Reg, true); PhysRegsUsed[Reg] = 0; AddToPhysRegsUseOrder(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
*SubRegs; ++SubRegs) {
if (PhysRegsUsed[*SubRegs] == -2) continue;
MF->getRegInfo().setPhysRegUsed(*SubRegs);
PhysRegsUsed[*SubRegs] = 0; AddToPhysRegsUseOrder(*SubRegs);
}
}
}
}
if (MI->isDebugValue() &&
MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
unsigned VirtReg = MI->getOperand(0).getReg();
if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) &&
!getVirt2PhysRegMapSlot(VirtReg))
MI->getOperand(0).setReg(0U);
}
SmallSet<unsigned, 4> ReloadedRegs;
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i, ReloadedRegs,
isCopy ? DstCopyReg : 0);
}
for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
unsigned VirtReg = Kills[i];
unsigned PhysReg = VirtReg;
if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
PhysReg = PhysRegSlot;
PhysRegSlot = 0;
} else if (PhysRegsUsed[PhysReg] == -2) {
continue;
} else {
assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
"Silently clearing a virtual register?");
}
if (!PhysReg) continue;
DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
<< "[%reg" << VirtReg <<"], removing it from live set\n");
removePhysReg(PhysReg);
for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
*SubRegs; ++SubRegs) {
if (PhysRegsUsed[*SubRegs] != -2) {
DEBUG(dbgs() << " Last use of "
<< TRI->getName(*SubRegs) << "[%reg" << VirtReg
<<"], removing it from live set\n");
removePhysReg(*SubRegs);
}
}
}
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef() || MO.isImplicit() || !MO.getReg() ||
MO.isEarlyClobber() ||
!TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
continue;
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
MF->getRegInfo().setPhysRegUsed(Reg);
spillPhysReg(MBB, MI, Reg, true); PhysRegsUsed[Reg] = 0; AddToPhysRegsUseOrder(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
*SubRegs; ++SubRegs) {
if (PhysRegsUsed[*SubRegs] == -2) continue;
MF->getRegInfo().setPhysRegUsed(*SubRegs);
PhysRegsUsed[*SubRegs] = 0; AddToPhysRegsUseOrder(*SubRegs);
}
}
if (TID.ImplicitDefs) {
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
*ImplicitDefs; ++ImplicitDefs) {
unsigned Reg = *ImplicitDefs;
if (PhysRegsUsed[Reg] != -2) {
spillPhysReg(MBB, MI, Reg, true);
AddToPhysRegsUseOrder(Reg);
PhysRegsUsed[Reg] = 0; }
MF->getRegInfo().setPhysRegUsed(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
*SubRegs; ++SubRegs) {
if (PhysRegsUsed[*SubRegs] == -2) continue;
AddToPhysRegsUseOrder(*SubRegs);
PhysRegsUsed[*SubRegs] = 0; MF->getRegInfo().setPhysRegUsed(*SubRegs);
}
}
}
SmallVector<unsigned, 8> DeadDefs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDead())
DeadDefs.push_back(MO.getReg());
}
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef() || !MO.getReg() ||
MO.isEarlyClobber() ||
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue;
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
if (isCopy &&
TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
isPhysRegAvailable(SrcCopyReg)) {
DestPhysReg = SrcCopyReg;
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
} else if (isCopy &&
TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
MF->getRegInfo().getRegClass(DestVirtReg)->
contains(SrcCopyPhysReg)) {
DestPhysReg = SrcCopyPhysReg;
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
} else
DestPhysReg = getReg(MBB, MI, DestVirtReg);
}
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
markVirtRegModified(DestVirtReg);
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
<< " to %reg" << DestVirtReg << "\n");
MO.setReg(DestPhysReg); }
for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
unsigned VirtReg = DeadDefs[i];
unsigned PhysReg = VirtReg;
if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
PhysReg = PhysRegSlot;
assert(PhysReg != 0);
PhysRegSlot = 0;
} else if (PhysRegsUsed[PhysReg] == -2) {
continue;
} else if (!PhysReg)
continue;
DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
<< " [%reg" << VirtReg
<< "] is never used, removing it from live set\n");
removePhysReg(PhysReg);
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
<< " [%reg" << *AliasSet
<< "] is never used, removing it from live set\n");
removePhysReg(*AliasSet);
}
}
}
if (TID.isCall())
for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
if (PhysRegsUsed[i] <= 0) continue;
unsigned VirtReg = PhysRegsUsed[i];
if (!isVirtRegModified(VirtReg)) continue;
DEBUG(dbgs() << " Storing dirty %reg" << VirtReg);
storeVirtReg(MBB, MI, VirtReg, i, false);
markVirtRegModified(VirtReg, false);
DEBUG(dbgs() << " because the call might throw\n");
}
if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
SrcCopySubReg, DstCopySubReg) &&
SrcCopyReg == DstCopyReg && DeadDefs.empty())
MBB.erase(MI);
}
MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
if (unsigned VirtReg = PhysRegsUsed[i])
spillVirtReg(MBB, MI, VirtReg, i);
else
removePhysReg(i);
}
#if 0
bool AllOk = true;
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
if (unsigned PR = Virt2PhysRegMap[i]) {
cerr << "Register still mapped: " << i << " -> " << PR << "\n";
AllOk = false;
}
assert(AllOk && "Virtual registers still in phys regs?");
#endif
PhysRegsUseOrder.clear();
}
bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
DEBUG(dbgs() << "Machine Function\n");
MF = &Fn;
TM = &Fn.getTarget();
TRI = TM->getRegisterInfo();
TII = TM->getInstrInfo();
PhysRegsUsed.assign(TRI->getNumRegs(), -1);
{
BitVector Allocable = TRI->getAllocatableSet(Fn);
for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
if (!Allocable[i])
PhysRegsUsed[i] = -2; }
unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
StackSlotForVirtReg.grow(LastVirtReg);
Virt2PhysRegMap.grow(LastVirtReg);
Virt2LastUseMap.grow(LastVirtReg);
VirtRegModified.resize(LastVirtReg+1 -
TargetRegisterInfo::FirstVirtualRegister);
UsedInMultipleBlocks.resize(LastVirtReg+1 -
TargetRegisterInfo::FirstVirtualRegister);
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB)
AllocateBasicBlock(*MBB);
StackSlotForVirtReg.clear();
PhysRegsUsed.clear();
VirtRegModified.clear();
UsedInMultipleBlocks.clear();
Virt2PhysRegMap.clear();
Virt2LastUseMap.clear();
return true;
}
FunctionPass *llvm::createLocalRegisterAllocator() {
return new RALocal();
}