#ifndef _MAXQ20_H_
#define _MAXQ20_H_
# define MAXQ10 0x0001
# define MAXQ20 0x0002
# define MAX (MAXQ10 | MAXQ20)
# define NOP_FMT 1
# define NOP_SRC 0x3A
# define NOP_DST 0x5A
typedef enum
{
ZEROBIT = 0x1,
ONEBIT = 0x2,
REG = 0x4,
MEM = 0x8,
IMM = 0x10,
DISP = 0x20,
BIT = 0x40,
FMT = 0x80,
IMMBIT = 0x100,
FLAG = 0x200,
DATA = 0x400,
BIT_BUCKET = 0x800,
}
UNKNOWN_OP;
typedef enum
{
NO_ARG = 0,
A_IMM = 0x01,
A_REG = 0x2,
A_MEM = 0x4,
FLAG_C = 0x8,
FLAG_NC = 0x10,
FLAG_Z = 0x20,
FLAG_NZ = 0x40,
FLAG_S = 0x80,
FLAG_E = 0x100,
FLAG_NE = 0x200,
ACC_BIT = 0x400,
DST_BIT = 0x800,
SRC_BIT = 0x1000,
A_BIT_0 = 0x2000,
A_BIT_1 = 0x4000,
A_DISP = 0x8000,
A_DATA = 0x10000,
A_BIT_BUCKET = 0x200000,
}
MAX_ARG_TYPE;
typedef struct
{
char * name;
unsigned int op_number;
MAX_ARG_TYPE arg[2];
int format;
int dst[2];
int src[2];
int arch;
unsigned int instr_id;
}
MAXQ20_OPCODE_INFO;
typedef struct
{
const MAXQ20_OPCODE_INFO *start;
const MAXQ20_OPCODE_INFO *end;
}
MAXQ20_OPCODES;
const MAXQ20_OPCODE_INFO op_table[] =
{
{"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0},
{REG | MEM | IMM | DISP, 0}, MAX, 0x11},
{"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39},
{"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0},
{REG | MEM | IMM | DISP, 0}, MAX, 0x12},
{"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A},
{"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0},
{REG | MEM | IMM | DISP, 0}, MAX, 0x13},
{"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B},
{"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21},
{"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D},
{"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29},
{"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22},
{"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23},
{"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26},
{"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24},
{"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25},
{"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F},
{"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E},
{"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B},
{"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A},
{"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C},
{"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D},
{"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x14},
{"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x16},
{"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x15},
{"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x17},
{"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0xA4},
{"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0xA5},
{"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0xA3},
{"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x50},
{"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x52},
{"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x56},
{"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x51},
{"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x55},
{"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53},
{"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57},
{"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0x54},
{"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68},
{"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A},
{"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E},
{"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69},
{"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D},
{"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C},
{"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78},
{"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A},
{"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E},
{"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79},
{"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D},
{"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C},
{"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0},
{REG | MEM | IMM | DISP, 0}, MAX, 0xD7},
{"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28},
{"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27},
{"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0},
{IMM | REG | MEM | DISP, 0}, MAX, 0xA0},
{"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0},
{"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0},
{"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT,
{REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80},
{"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E},
{"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D},
{"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D},
{"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F},
{"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40},
{"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41},
{"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97},
{"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D},
{NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00}
};
#define MOD0 0x0
#define MOD1 0x1
#define MOD2 0x2
#define MOD3 0x3
#define MOD4 0x4
#define MOD5 0x5
#define MOD6 0x6
#define MOD7 0x7
#define MOD8 0x8
#define MOD9 0x9
#define MODA 0xa
#define MODB 0xb
#define MODC 0xc
#define MODD 0xd
#define MODE 0xe
#define MODF 0xf
#define MOD10 0x10
#define MOD11 0x11
#define MOD12 0x12
#define MOD13 0x13
#define MOD14 0x14
#define MOD15 0x15
#define MOD16 0x16
#define MOD17 0x17
#define MOD18 0x18
#define MOD19 0x19
#define MOD1A 0x1a
#define MOD1B 0x1b
#define MOD1C 0x1c
#define MOD1D 0x1d
#define MOD1E 0x1e
#define MOD1F 0x1f
#define CTRL MOD8
#define ACC MOD9
#define Act_ACC MODA
#define PFX MODB
#define IP MODC
#define SPIV MODD
#define LC MODD
#define DP MODF
typedef enum _Reg_type
{ Reg_8R,
Reg_16R,
Reg_8W,
Reg_16W
}
Reg_type;
typedef struct reg
{
char *reg_name;
short int Mod_name;
short int Mod_index;
int opcode;
Reg_type rtype;
int arch;
}
reg_entry;
reg_entry *new_reg_table = NULL;
int num_of_reg = 0;
typedef struct
{
char *rname;
int rindex;
}
reg_index;
reg_entry system_reg_table[] =
{
{
"AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX},
{
"APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX},
{
"PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX},
{
"IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX},
{
"IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX},
{
"SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX},
{
"IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX},
{
"CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX},
{
"WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX},
{
"A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20},
{
"A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20},
{
"A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20},
{
"A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20},
{
"A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20},
{
"A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20},
{
"A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20},
{
"A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20},
{
"A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20},
{
"A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20},
{
"A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20},
{
"A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20},
{
"A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20},
{
"A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20},
{
"A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20},
{
"A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20},
{
"ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20},
{
"A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20},
{
"A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10},
{
"A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10},
{
"A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10},
{
"A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10},
{
"A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10},
{
"A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10},
{
"A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10},
{
"A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10},
{
"A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10},
{
"A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10},
{
"A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10},
{
"A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10},
{
"A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10},
{
"A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10},
{
"A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10},
{
"A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10},
{
"A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10},
{
"ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10},
{
"PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX},
{
"PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX},
{
"PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX},
{
"PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX},
{
"PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX},
{
"PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX},
{
"PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX},
{
"PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX},
{
"IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX},
{
"SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX},
{
"IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX},
{
"LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX},
{
"LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX},
{
"OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX},
{
"DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX},
{
"GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX},
{
"GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX},
{
"BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX},
{
"GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX},
{
"GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX},
{
"GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX},
{
"FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX},
{
"DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX},
{
"DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX},
};
typedef struct
{
char *name;
int type;
}
match_table;
#define GPIO0 0x00
#define GPIO1 0x01
#define RTC 0x00
#define MAC 0x02
#define SER0 0x02
#define SPI 0x03
#define OWBM 0x03
#define SER1 0x03
#define TIMER20 0x03
#define TIMER21 0x04
#define JTAGD 0x03
#define LCD 0x03
reg_entry peripheral_reg_table[] =
{
{
"PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX},
{
"PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX},
{
"PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX},
{
"PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX},
{
"EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX},
{
"EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX},
{
"PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX},
{
"PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX},
{
"PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX},
{
"PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX},
{
"EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX},
{
"PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX},
{
"PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX},
{
"PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX},
{
"PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX},
{
"RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX},
{
"RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX},
{
"RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX},
{
"RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX},
{
"RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX},
{
"RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX},
{
"RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX},
{
"PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX},
{
"PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX},
{
"PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX},
{
"PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX},
{
"EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX},
{
"EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX},
{
"PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX},
{
"PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX},
{
"PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX},
{
"PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX},
{
"EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX},
{
"PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX},
{
"PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX},
{
"PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX},
{
"PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX},
#if 0
{
"SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX},
{
"WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX},
#endif
{
"MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX},
{
"MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX},
{
"MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX},
{
"MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX},
{
"MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX},
{
"MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX},
{
"SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX},
{
"SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX},
{
"SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX},
{
"PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX},
{
"LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX},
{
"LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX},
{
"LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX},
{
"LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX},
{
"LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX},
{
"LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX},
{
"LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX},
{
"LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX},
{
"LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX},
{
"LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX},
{
"LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX},
{
"LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX},
{
"LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX},
{
"LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX},
{
"LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX},
{
"LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX},
{
"LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX},
{
"LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX},
{
"LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX},
{
"SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX},
{
"SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX},
{
"SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX},
{
"SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX},
{
"OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX},
{
"OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX},
{
"SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX},
{
"SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX},
{
"SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX},
{
"PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX},
{
"T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX},
{
"T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX},
{
"T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX},
{
"T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX},
{
"T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX},
{
"T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX},
{
"T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX},
{
"T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX},
{
"T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX},
{
"T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX},
{
"T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX},
{
"T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX},
{
"T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX},
{
"T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX},
{
"T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX},
{
"T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX},
{
"T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX},
{
"T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX},
{
"T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX},
{
"T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX},
{
"T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX},
{
"T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX},
{
"T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX},
{
"T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX},
{
"T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX},
{
"T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX},
{
"T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX},
{
NULL, 0, 0, 0, 0, 0}
};
struct mem_access
{
char *name;
int opcode;
};
typedef struct mem_access mem_access;
struct mem_access mem_table[] =
{
{"@SP--", 0x0d},
{"@DP[0]", 0x0f},
{"@DP[1]", 0x4f},
{"@DP[0]++", 0x1f},
{"@DP[1]++", 0x5f},
{"@DP[0]--", 0x2f},
{"@DP[1]--", 0x6f},
{"@BP[OFFS]", 0x0E},
{"@BP[OFFS++]", 0x1E},
{"@BP[OFFS--]", 0x2E},
{"NUL", 0x76},
{"@++SP", 0x0D},
{"@BP[++OFFS]", 0x1E},
{"@BP[--OFFS]", 0x2E},
{"@++DP[0]", 0x1F},
{"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F}
};
struct reg_bit
{
reg_entry *reg;
int bit;
};
typedef struct reg_bit reg_bit;
struct bit_name
{
char *name;
char *reg_bit;
};
typedef struct bit_name bit_name;
bit_name bit_table[] =
{
{
"RI", "SCON.0"},
{
"MOD0", "APC.0"},
{
"MOD1", "APC.1"},
{
"MOD2", "APC.2"},
{
"IDS", "APC.6"},
{
"CLR", "APC.6"},
{
"E", "PSF.0"},
{
"C", "PSF.1"},
{
"OV", "PSF.2"},
{
"S", "PSF.6"},
{
"Z", "PSF.7"},
{
"IGE", "IC.0"},
{
"INS", "IC.1"},
{
"CGDS", "IC.5"},
{
"IM0", "IMR.0"},
{
"IM1", "IMR.1"},
{
"IM2", "IMR.2"},
{
"IM3", "IMR.3"},
{
"IM4", "IMR.4"},
{
"IM5", "IMR.5"},
{
"IMS", "IMR.7"},
{
"PWL", "SC.1"},
{
"ROD", "SC.2"},
{
"UPA", "SC.3"},
{
"CDA0", "SC.4"},
{
"CDA1", "SC.5"},
{
"II0", "IIR.0"},
{
"II1", "IIR.1"},
{
"II2", "IIR.2"},
{
"II3", "IIR.3"},
{
"II4", "IIR.4"},
{
"II5", "IIR.5"},
{
"IIS", "IIR.7"},
{
"CD0", "CKCN.0"},
{
"CD1", "CKCN.1"},
{
"PMME", "CKCN.2"},
{
"SWB", "CKCN.3"},
{
"STOP", "CKCN.4"},
{
"RGMD", "CKCN.5"},
{
"RGSL", "CKCN.6"},
{
"RWT", "WDCN.0"},
{
"EWT", "WDCN.1"},
{
"WTRF", "WDCN.2"},
{
"WDIF", "WDCN.3"},
{
"WD0", "WDCN.4"},
{
"WD1", "WDCN.5"},
{
"EWDI", "WDCN.6"},
{
"POR", "WDCN.7"},
{
"DPS0", "DPC.0"},
{
"DPS1", "DPC.1"},
{
"WBS0", "DPC.2"},
{
"WBS1", "DPC.3"},
{
"WBS2", "DPC.4"},
{
"TI", "SCON.1"},
{
"RB8", "SCON.2"},
{
"TB8", "SCON.3"},
{
"REN", "SCON.4"},
{
"SM2", "SCON.5"},
{
"SM1", "SCON.6"},
{
"SM0", "SCON.7"},
{
"FE", "SCON.7"}
};
const char *LSInstr[] =
{
"LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP",
"DJNZ", "CALL", NULL
};
typedef enum
{
DST,
SRC,
BOTH,
}
type1;
struct mem_access_syntax
{
char name[12];
type1 type;
char *invalid_op[5];
};
typedef struct mem_access_syntax mem_access_syntax;
const mem_access_syntax mem_access_syntax_table[] =
{
{
"@SP--", SRC,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@DP[0]", BOTH,
{
"@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
{
"@DP[1]", BOTH,
{
"@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
{
"@DP[0]++", SRC,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@DP[1]++", SRC,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@DP[0]--", SRC,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@DP[1]--", SRC,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@BP[OFFS]", BOTH,
{
"@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}},
{
"@BP[OFFS++]", SRC,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@BP[OFFS--]", SRC,
{
NULL, NULL, NULL, NULL, NULL}},
{
"NUL", DST,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@++SP", DST,
{
NULL, NULL, NULL, NULL, NULL}},
{
"@BP[++OFFS]", DST,
{
"@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
{
"@BP[--OFFS]", DST,
{
"@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
{
"@++DP[0]", DST,
{
"@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
{
"@++DP[1]", DST,
{
"@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
{
"@--DP[0]", DST,
{
"@DP[0]++", "@DP[0]--", NULL, NULL, NULL}},
{
"@--DP[1]", DST,
{
"@DP[1]++", "@DP[1]--", NULL, NULL, NULL}}
};
#endif