#ifndef GCC_ARM_H
#define GCC_ARM_H
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
if (TARGET_ARM) \
builtin_define ("__arm__"); \
else \
builtin_define ("__thumb__"); \
\
if (TARGET_BIG_END) \
{ \
builtin_define ("__ARMEB__"); \
if (TARGET_THUMB) \
builtin_define ("__THUMBEB__"); \
if (TARGET_LITTLE_WORDS) \
builtin_define ("__ARMWEL__"); \
} \
else \
{ \
builtin_define ("__ARMEL__"); \
if (TARGET_THUMB) \
builtin_define ("__THUMBEL__"); \
} \
\
if (TARGET_APCS_32) \
builtin_define ("__APCS_32__"); \
else \
builtin_define ("__APCS_26__"); \
\
if (TARGET_SOFT_FLOAT) \
builtin_define ("__SOFTFP__"); \
\
\
if (TARGET_VFP && !TARGET_HARD_FLOAT) \
builtin_define ("__VFP_FP__"); \
\
\
if (TARGET_INTERWORK) \
builtin_define ("__THUMB_INTERWORK__"); \
\
builtin_assert ("cpu=arm"); \
builtin_assert ("machine=arm"); \
} while (0)
#define TARGET_CPU_arm2 0x0000
#define TARGET_CPU_arm250 0x0000
#define TARGET_CPU_arm3 0x0000
#define TARGET_CPU_arm6 0x0001
#define TARGET_CPU_arm600 0x0001
#define TARGET_CPU_arm610 0x0002
#define TARGET_CPU_arm7 0x0001
#define TARGET_CPU_arm7m 0x0004
#define TARGET_CPU_arm7dm 0x0004
#define TARGET_CPU_arm7dmi 0x0004
#define TARGET_CPU_arm700 0x0001
#define TARGET_CPU_arm710 0x0002
#define TARGET_CPU_arm7100 0x0002
#define TARGET_CPU_arm7500 0x0002
#define TARGET_CPU_arm7500fe 0x1001
#define TARGET_CPU_arm7tdmi 0x0008
#define TARGET_CPU_arm8 0x0010
#define TARGET_CPU_arm810 0x0020
#define TARGET_CPU_strongarm 0x0040
#define TARGET_CPU_strongarm110 0x0040
#define TARGET_CPU_strongarm1100 0x0040
#define TARGET_CPU_arm9 0x0080
#define TARGET_CPU_arm9tdmi 0x0080
#define TARGET_CPU_xscale 0x0100
#define TARGET_CPU_generic 0x8000
typedef enum arm_cond_code
{
ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
}
arm_cc;
extern arm_cc arm_current_cc;
#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
extern int arm_target_label;
extern int arm_ccfsm_state;
extern GTY(()) rtx arm_target_insn;
extern int target_flags;
extern const char * target_fp_name;
extern GTY(()) rtx arm_compare_op0;
extern GTY(()) rtx arm_compare_op1;
extern rtx pool_vector_label;
extern int return_used_this_function;
extern GTY(()) rtx aof_pic_label;
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT TARGET_CPU_generic
#endif
#if TARGET_CPU_DEFAULT == TARGET_CPU_generic
#undef TARGET_CPU_DEFAULT
#ifdef SUBTARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
#else
#define TARGET_CPU_DEFAULT TARGET_CPU_arm6
#endif
#endif
#if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
#else
#if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
#else
#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
#else
#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
#else
#if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
#else
#if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
#else
Unrecognized value in TARGET_CPU_DEFAULT.
#endif
#endif
#endif
#endif
#endif
#endif
#undef CPP_SPEC
#define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
%{mapcs-32:%{mapcs-26: \
%e-mapcs-26 and -mapcs-32 may not be used together}} \
%{msoft-float:%{mhard-float: \
%e-msoft-float and -mhard_float may not be used together}} \
%{mbig-endian:%{mlittle-endian: \
%e-mbig-endian and -mlittle-endian may not be used together}}"
#define CPP_CPU_ARCH_SPEC "\
%{march=arm2:-D__ARM_ARCH_2__} \
%{march=arm250:-D__ARM_ARCH_2__} \
%{march=arm3:-D__ARM_ARCH_2__} \
%{march=arm6:-D__ARM_ARCH_3__} \
%{march=arm600:-D__ARM_ARCH_3__} \
%{march=arm610:-D__ARM_ARCH_3__} \
%{march=arm7:-D__ARM_ARCH_3__} \
%{march=arm700:-D__ARM_ARCH_3__} \
%{march=arm710:-D__ARM_ARCH_3__} \
%{march=arm720:-D__ARM_ARCH_3__} \
%{march=arm7100:-D__ARM_ARCH_3__} \
%{march=arm7500:-D__ARM_ARCH_3__} \
%{march=arm7500fe:-D__ARM_ARCH_3__} \
%{march=arm7m:-D__ARM_ARCH_3M__} \
%{march=arm7dm:-D__ARM_ARCH_3M__} \
%{march=arm7dmi:-D__ARM_ARCH_3M__} \
%{march=arm7tdmi:-D__ARM_ARCH_4T__} \
%{march=arm8:-D__ARM_ARCH_4__} \
%{march=arm810:-D__ARM_ARCH_4__} \
%{march=arm9:-D__ARM_ARCH_4T__} \
%{march=arm920:-D__ARM_ARCH_4__} \
%{march=arm920t:-D__ARM_ARCH_4T__} \
%{march=arm9tdmi:-D__ARM_ARCH_4T__} \
%{march=strongarm:-D__ARM_ARCH_4__} \
%{march=strongarm110:-D__ARM_ARCH_4__} \
%{march=strongarm1100:-D__ARM_ARCH_4__} \
%{march=xscale:-D__ARM_ARCH_5TE__} \
%{march=xscale:-D__XSCALE__} \
%{march=armv2:-D__ARM_ARCH_2__} \
%{march=armv2a:-D__ARM_ARCH_2__} \
%{march=armv3:-D__ARM_ARCH_3__} \
%{march=armv3m:-D__ARM_ARCH_3M__} \
%{march=armv4:-D__ARM_ARCH_4__} \
%{march=armv4t:-D__ARM_ARCH_4T__} \
%{march=armv5:-D__ARM_ARCH_5__} \
%{march=armv5t:-D__ARM_ARCH_5T__} \
%{march=armv5e:-D__ARM_ARCH_5E__} \
%{march=armv5te:-D__ARM_ARCH_5TE__} \
%{!march=*: \
%{mcpu=arm2:-D__ARM_ARCH_2__} \
%{mcpu=arm250:-D__ARM_ARCH_2__} \
%{mcpu=arm3:-D__ARM_ARCH_2__} \
%{mcpu=arm6:-D__ARM_ARCH_3__} \
%{mcpu=arm600:-D__ARM_ARCH_3__} \
%{mcpu=arm610:-D__ARM_ARCH_3__} \
%{mcpu=arm7:-D__ARM_ARCH_3__} \
%{mcpu=arm700:-D__ARM_ARCH_3__} \
%{mcpu=arm710:-D__ARM_ARCH_3__} \
%{mcpu=arm720:-D__ARM_ARCH_3__} \
%{mcpu=arm7100:-D__ARM_ARCH_3__} \
%{mcpu=arm7500:-D__ARM_ARCH_3__} \
%{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
%{mcpu=arm7m:-D__ARM_ARCH_3M__} \
%{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
%{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
%{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
%{mcpu=arm8:-D__ARM_ARCH_4__} \
%{mcpu=arm810:-D__ARM_ARCH_4__} \
%{mcpu=arm9:-D__ARM_ARCH_4T__} \
%{mcpu=arm920:-D__ARM_ARCH_4__} \
%{mcpu=arm920t:-D__ARM_ARCH_4T__} \
%{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
%{mcpu=strongarm:-D__ARM_ARCH_4__} \
%{mcpu=strongarm110:-D__ARM_ARCH_4__} \
%{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
%{mcpu=xscale:-D__ARM_ARCH_5TE__} \
%{mcpu=xscale:-D__XSCALE__} \
%{!mcpu*:%(cpp_cpu_arch_default)}} \
"
#ifndef CC1_SPEC
#define CC1_SPEC ""
#endif
#define EXTRA_SPECS \
{ "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
{ "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
SUBTARGET_EXTRA_SPECS
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif
#ifndef TARGET_VERSION
#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
#endif
#define ARM_FLAG_APCS_FRAME (1 << 0)
#define ARM_FLAG_POKE (1 << 1)
#define ARM_FLAG_FPE (1 << 2)
#define ARM_FLAG_APCS_32 (1 << 3)
#define ARM_FLAG_APCS_STACK (1 << 4)
#define ARM_FLAG_APCS_FLOAT (1 << 5)
#define ARM_FLAG_APCS_REENT (1 << 6)
#define ARM_FLAG_MMU_TRAPS (1 << 7)
#define ARM_FLAG_SOFT_FLOAT (1 << 8)
#define ARM_FLAG_BIG_END (1 << 9)
#define ARM_FLAG_INTERWORK (1 << 10)
#define ARM_FLAG_LITTLE_WORDS (1 << 11)
#define ARM_FLAG_NO_SCHED_PRO (1 << 12)
#define ARM_FLAG_ABORT_NORETURN (1 << 13)
#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
#define ARM_FLAG_LONG_CALLS (1 << 15)
#define ARM_FLAG_THUMB (1 << 16)
#define THUMB_FLAG_BACKTRACE (1 << 17)
#define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
#define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
#define ARM_FLAG_VFP (1 << 21)
#define ARM_FLAG_ATPCS (1 << 22)
#define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
#define TARGET_FPE (target_flags & ARM_FLAG_FPE)
#define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
#define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
#define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_VFP (target_flags & ARM_FLAG_VFP)
#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
#define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
#define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
#define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
#define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
#define TARGET_ARM (! TARGET_THUMB)
#define TARGET_EITHER 1
#define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
#define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
#define TARGET_BACKTRACE (leaf_function_p () \
? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
: (target_flags & THUMB_FLAG_BACKTRACE))
#ifndef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES
#endif
#define TARGET_SWITCHES \
{ \
{"apcs", ARM_FLAG_APCS_FRAME, "" }, \
{"apcs-frame", ARM_FLAG_APCS_FRAME, \
N_("Generate APCS conformant stack frames") }, \
{"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
{"poke-function-name", ARM_FLAG_POKE, \
N_("Store function names in object code") }, \
{"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
{"fpe", ARM_FLAG_FPE, "" }, \
{"apcs-32", ARM_FLAG_APCS_32, \
N_("Use the 32-bit version of the APCS") }, \
{"apcs-26", -ARM_FLAG_APCS_32, \
N_("Use the 26-bit version of the APCS") }, \
{"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
{"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
{"apcs-float", ARM_FLAG_APCS_FLOAT, \
N_("Pass FP arguments in FP registers") }, \
{"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
{"apcs-reentrant", ARM_FLAG_APCS_REENT, \
N_("Generate re-entrant, PIC code") }, \
{"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
{"alignment-traps", ARM_FLAG_MMU_TRAPS, \
N_("The MMU will trap on unaligned accesses") }, \
{"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
{"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
{"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
{"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
{"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
{"soft-float", ARM_FLAG_SOFT_FLOAT, \
N_("Use library calls to perform FP operations") }, \
{"hard-float", -ARM_FLAG_SOFT_FLOAT, \
N_("Use hardware floating point instructions") }, \
{"big-endian", ARM_FLAG_BIG_END, \
N_("Assume target CPU is configured as big endian") }, \
{"little-endian", -ARM_FLAG_BIG_END, \
N_("Assume target CPU is configured as little endian") }, \
{"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
N_("Assume big endian bytes, little endian words") }, \
{"thumb-interwork", ARM_FLAG_INTERWORK, \
N_("Support calls between Thumb and ARM instruction sets") }, \
{"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
{"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
N_("Generate a call to abort if a noreturn function returns")}, \
{"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
{"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
N_("Do not move instructions into a function's prologue") }, \
{"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
{"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
N_("Do not load the PIC register in function prologues") }, \
{"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
{"long-calls", ARM_FLAG_LONG_CALLS, \
N_("Generate call insns as indirect calls, if necessary") }, \
{"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
{"thumb", ARM_FLAG_THUMB, \
N_("Compile for the Thumb not the ARM") }, \
{"no-thumb", -ARM_FLAG_THUMB, "" }, \
{"arm", -ARM_FLAG_THUMB, "" }, \
{"tpcs-frame", THUMB_FLAG_BACKTRACE, \
N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
{"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
{"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
{"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
{"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
N_("Thumb: Assume non-static functions may be called from ARM code") }, \
{"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
"" }, \
{"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
{"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
"" }, \
SUBTARGET_SWITCHES \
{"", TARGET_DEFAULT, "" } \
}
#define TARGET_OPTIONS \
{ \
{"cpu=", & arm_select[0].string, \
N_("Specify the name of the target CPU") }, \
{"arch=", & arm_select[1].string, \
N_("Specify the name of the target architecture") }, \
{"tune=", & arm_select[2].string, "" }, \
{"fpe=", & target_fp_name, "" }, \
{"fp=", & target_fp_name, \
N_("Specify the version of the floating point emulator") }, \
{"structure-size-boundary=", & structure_size_string, \
N_("Specify the minimum bit alignment of structures") }, \
{"pic-register=", & arm_pic_register_string, \
N_("Specify the register to be used for PIC addressing") } \
}
struct arm_cpu_select
{
const char * string;
const char * name;
const struct processors * processors;
};
extern struct arm_cpu_select arm_select[];
enum prog_mode_type
{
prog_mode26,
prog_mode32
};
#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
extern enum prog_mode_type arm_prgmode;
enum floating_point_type
{
FP_HARD,
FP_SOFT2,
FP_SOFT3
};
#define arm_fpu_attr ((enum attr_fpu) arm_fpu)
extern enum floating_point_type arm_fpu;
extern enum floating_point_type arm_fpu_arch;
#ifndef FP_DEFAULT
#define FP_DEFAULT FP_SOFT2
#endif
extern int arm_fast_multiply;
extern int arm_arch4;
extern int arm_arch5;
extern int arm_arch5e;
extern int arm_ld_sched;
extern int thumb_code;
extern int arm_is_strong;
extern int arm_is_xscale;
extern int arm_is_6_or_7;
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
#endif
#define CAN_DEBUG_WITHOUT_FP
#undef TARGET_MEM_FUNCTIONS
#define TARGET_MEM_FUNCTIONS 1
#define OVERRIDE_OPTIONS arm_override_options ()
#ifndef NEED_GOT_RELOC
#define NEED_GOT_RELOC 0
#endif
#ifndef NEED_PLT_RELOC
#define NEED_PLT_RELOC 0
#endif
#ifndef GOT_PCREL
#define GOT_PCREL 1
#endif
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
{ \
if (MODE == QImode) \
UNSIGNEDP = 1; \
else if (MODE == HImode) \
UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
(MODE) = SImode; \
}
#define PROMOTE_FUNCTION_ARGS
#define ENABLE_XF_PATTERNS 0
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
#if defined(__ARMEB__) && !defined(__ARMWEL__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif
#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
#define UNITS_PER_WORD 4
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
#define FUNCTION_BOUNDARY 32
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
#define EMPTY_FIELD_BOUNDARY 32
#define BIGGEST_ALIGNMENT 32
#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
extern int arm_structure_size_boundary;
#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
#endif
extern const char * structure_size_string;
#define STRICT_ALIGNMENT 1
#define FIXED_REGISTERS \
{ \
0,0,0,0,0,0,0,0, \
0,0,0,0,0,1,0,1, \
0,0,0,0,0,0,0,0, \
1,1,1 \
}
#define CALL_USED_REGISTERS \
{ \
1,1,1,1,0,0,0,0, \
0,0,0,0,1,1,1,1, \
1,1,1,1,0,0,0,0, \
1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
#endif
#define CONDITIONAL_REGISTER_USAGE \
{ \
int regno; \
\
if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
{ \
for (regno = FIRST_ARM_FP_REGNUM; \
regno <= LAST_ARM_FP_REGNUM; ++regno) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
} \
else if (TARGET_APCS_STACK) \
{ \
fixed_regs[10] = 1; \
call_used_regs[10] = 1; \
} \
if (TARGET_APCS_FRAME) \
{ \
fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
} \
SUBTARGET_CONDITIONAL_REGISTER_USAGE \
}
#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
case '@': \
fputs (ASM_COMMENT_START, FILE); \
break; \
\
case 'r': \
fputs (REGISTER_PREFIX, FILE); \
fputs (reg_names [va_arg (ARGS, int)], FILE); \
break;
#define ROUND_UP(X) (((X) + 3) & ~3)
#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define ARM_NUM_REGS(MODE) \
ARM_NUM_INTS (GET_MODE_SIZE (MODE))
#define ARM_NUM_REGS2(MODE, TYPE) \
ARM_NUM_INTS ((MODE) == BLKmode ? \
int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
#define NUM_ARG_REGS 4
#define ARG_REGISTER(N) (N - 1)
#if 0
#define STRUCT_VALUE 0
#else
#define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
#endif
#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
#define LAST_LO_REGNUM 7
#define EXCEPTION_LR_REGNUM 2
#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
#define ARM_HARD_FRAME_POINTER_REGNUM 11
#define THUMB_HARD_FRAME_POINTER_REGNUM 7
#define HARD_FRAME_POINTER_REGNUM \
(TARGET_ARM \
? ARM_HARD_FRAME_POINTER_REGNUM \
: THUMB_HARD_FRAME_POINTER_REGNUM)
#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
#define STACK_POINTER_REGNUM SP_REGNUM
#define FIRST_ARM_FP_REGNUM 16
#define LAST_ARM_FP_REGNUM 23
#define FRAME_POINTER_REGNUM 25
#define ARG_POINTER_REGNUM 26
#define FIRST_PSEUDO_REGISTER 27
#define FRAME_POINTER_REQUIRED \
(current_function_has_nonlocal_label \
|| (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
#define HARD_REGNO_NREGS(REGNO, MODE) \
((TARGET_ARM \
&& REGNO >= FIRST_ARM_FP_REGNUM \
&& REGNO != FRAME_POINTER_REGNUM \
&& REGNO != ARG_POINTER_REGNUM) \
? 1 : ARM_NUM_REGS (MODE))
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
arm_hard_regno_mode_ok ((REGNO), (MODE))
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
#define REG_ALLOC_ORDER \
{ \
3, 2, 1, 0, 12, 14, 4, 5, \
6, 7, 8, 10, 9, 11, 13, 15, \
16, 17, 18, 19, 20, 21, 22, 23, \
24, 25, 26 \
}
#define HARD_REGNO_RENAME_OK(SRC, DST) \
(! IS_INTERRUPT (cfun->machine->func_type) || \
regs_ever_live[DST])
enum reg_class
{
NO_REGS,
FPU_REGS,
LO_REGS,
STACK_REG,
BASE_REGS,
HI_REGS,
CC_REG,
GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"FPU_REGS", \
"LO_REGS", \
"STACK_REG", \
"BASE_REGS", \
"HI_REGS", \
"CC_REG", \
"GENERAL_REGS", \
"ALL_REGS", \
}
#define REG_CLASS_CONTENTS \
{ \
{ 0x0000000 }, \
{ 0x0FF0000 }, \
{ 0x00000FF }, \
{ 0x0002000 }, \
{ 0x00020FF }, \
{ 0x000FF00 }, \
{ 0x1000000 }, \
{ 0x200FFFF }, \
{ 0x2FFFFFF } \
}
#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
#define MODE_BASE_REG_CLASS(MODE) \
(TARGET_ARM ? GENERAL_REGS : \
(((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
#define SMALL_REGISTER_CLASSES TARGET_THUMB
#define REG_CLASS_FROM_LETTER(C) \
( (C) == 'f' ? FPU_REGS \
: (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
: TARGET_ARM ? NO_REGS \
: (C) == 'h' ? HI_REGS \
: (C) == 'b' ? BASE_REGS \
: (C) == 'k' ? STACK_REG \
: (C) == 'c' ? CC_REG \
: NO_REGS)
#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
((C) == 'I' ? const_ok_for_arm (VALUE) : \
(C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
(C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
(C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
(C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
|| (((VALUE) & ((VALUE) - 1)) == 0)) \
: 0)
#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
(C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
(C) == 'K' ? thumb_shiftable_const (VAL) : \
(C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
(C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
&& ((VAL) & 3) == 0) : \
(C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
(C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
: 0)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
(TARGET_ARM ? \
CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
(C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
(TARGET_ARM ? \
CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
#define EXTRA_CONSTRAINT_ARM(OP, C) \
((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
(C) == 'R' ? (GET_CODE (OP) == MEM \
&& GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
&& CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
(C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
: 0)
#define EXTRA_CONSTRAINT_THUMB(X, C) \
((C) == 'Q' ? (GET_CODE (X) == MEM \
&& GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
#define EXTRA_CONSTRAINT(X, C) \
(TARGET_ARM ? \
EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
(TARGET_ARM ? (CLASS) : \
((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
? ((true_regnum (X) == -1 ? LO_REGS \
: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
: NO_REGS)) \
: NO_REGS)
#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
((CLASS) != LO_REGS \
? ((true_regnum (X) == -1 ? LO_REGS \
: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
: NO_REGS)) \
: NO_REGS)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
(TARGET_ARM ? \
(((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
(TARGET_ARM ? \
(((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
do \
{ \
if (GET_CODE (X) == PLUS \
&& GET_CODE (XEXP (X, 0)) == REG \
&& REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
&& REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT) \
{ \
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
HOST_WIDE_INT low, high; \
\
if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
low = ((val & 0xf) ^ 0x8) - 0x8; \
else if (MODE == SImode \
|| (MODE == SFmode && TARGET_SOFT_FLOAT) \
|| ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
\
low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
\
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
&& TARGET_HARD_FLOAT) \
\
low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
else \
break; \
\
high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
^ (unsigned HOST_WIDE_INT) 0x80000000) \
- (unsigned HOST_WIDE_INT) 0x80000000); \
\
if (low == 0 || high == 0 || (high + low != val)) \
break; \
\
\
X = gen_rtx_PLUS (GET_MODE (X), \
gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
GEN_INT (high)), \
GEN_INT (low)); \
push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
VOIDmode, 0, 0, OPNUM, TYPE); \
goto WIN; \
} \
} \
while (0)
#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
{ \
if (GET_CODE (X) == PLUS \
&& GET_MODE_SIZE (MODE) < 4 \
&& GET_CODE (XEXP (X, 0)) == REG \
&& XEXP (X, 0) == stack_pointer_rtx \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
{ \
rtx orig_X = X; \
X = copy_rtx (X); \
push_reload (orig_X, NULL_RTX, &X, NULL, \
MODE_BASE_REG_CLASS (MODE), \
Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
goto WIN; \
} \
}
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
if (TARGET_ARM) \
ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
else \
THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
#define CLASS_MAX_NREGS(CLASS, MODE) \
((CLASS) == FPU_REGS ? 1 : ARM_NUM_REGS (MODE))
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
(TARGET_ARM ? \
((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
(FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
: \
((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
#define STARTING_FRAME_OFFSET 0
#define ACCUMULATE_OUTGOING_ARGS 1
#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
#define LIBCALL_VALUE(MODE) \
(TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
: gen_rtx_REG (MODE, ARG_REGISTER (1)))
#define FUNCTION_VALUE(VALTYPE, FUNC) \
LIBCALL_VALUE (TYPE_MODE (VALTYPE))
#define FUNCTION_VALUE_REGNO_P(REGNO) \
((REGNO) == ARG_REGISTER (1) \
|| (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
#define DEFAULT_PCC_STRUCT_RETURN 0
#define CALL_NORMAL 0x00000000
#define CALL_LONG 0x00000001
#define CALL_SHORT 0x00000002
#define ARM_FT_UNKNOWN 0
#define ARM_FT_NORMAL 1
#define ARM_FT_INTERWORKED 2
#define ARM_FT_EXCEPTION_HANDLER 3
#define ARM_FT_ISR 4
#define ARM_FT_FIQ 5
#define ARM_FT_EXCEPTION 6
#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
#define ARM_FT_INTERRUPT (1 << 2)
#define ARM_FT_NAKED (1 << 3)
#define ARM_FT_VOLATILE (1 << 4)
#define ARM_FT_NESTED (1 << 5)
#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
#define IS_NAKED(t) (t & ARM_FT_NAKED)
#define IS_NESTED(t) (t & ARM_FT_NESTED)
typedef struct machine_function GTY(())
{
rtx eh_epilogue_sp_ofs;
int far_jump_used;
int arg_pointer_live;
int lr_save_eliminated;
int frame_size;
unsigned long func_type;
int uses_anonymous_args;
}
machine_function;
typedef struct
{
int nregs;
int call_cookie;
} CUMULATIVE_ARGS;
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
( NUM_ARG_REGS > (CUM).nregs \
&& (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
? NUM_ARG_REGS - (CUM).nregs : 0)
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
(CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
#define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
#define EXPAND_BUILTIN_VA_ARG(valist, type) \
arm_va_arg (valist, type)
#define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
{ \
cfun->machine->uses_anonymous_args = 1; \
if ((CUM).nregs < NUM_ARG_REGS) \
(PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
}
#ifndef ARM_MCOUNT_NAME
#define ARM_MCOUNT_NAME "*mcount"
#endif
#ifndef ARM_FUNCTION_PROFILER
#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
{ \
char temp[20]; \
rtx sym; \
\
asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
IP_REGNUM, LR_REGNUM); \
assemble_name (STREAM, ARM_MCOUNT_NAME); \
fputc ('\n', STREAM); \
ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
assemble_aligned_integer (UNITS_PER_WORD, sym); \
}
#endif
#ifdef THUMB_FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM, LABELNO) \
if (TARGET_ARM) \
ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
else \
THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
#else
#define FUNCTION_PROFILER(STREAM, LABELNO) \
ARM_FUNCTION_PROFILER (STREAM, LABELNO)
#endif
#define EXIT_IGNORE_STACK 1
#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
#define USE_RETURN_INSN(ISCOND) \
(TARGET_ARM ? use_return_insn (ISCOND) : 0)
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
{ ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
{ ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
{ FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
{ FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
#define CAN_ELIMINATE(FROM, TO) \
(((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1)
#define THUMB_REG_PUSHED_P(reg) \
(regs_ever_live [reg] \
&& (! call_used_regs [reg] \
|| (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
&& !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
#define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
do \
{ \
(OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
} \
while (0)
#define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
{ \
(OFFSET) = 0; \
if ((FROM) == ARG_POINTER_REGNUM) \
{ \
int count_regs = 0; \
int regno; \
for (regno = 8; regno < 13; regno ++) \
if (THUMB_REG_PUSHED_P (regno)) \
count_regs ++; \
if (count_regs) \
(OFFSET) += 4 * count_regs; \
count_regs = 0; \
for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
if (THUMB_REG_PUSHED_P (regno)) \
count_regs ++; \
if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
(OFFSET) += 4 * (count_regs + 1); \
if (TARGET_BACKTRACE) \
{ \
if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
(OFFSET) += 20; \
else \
(OFFSET) += 16; \
} \
} \
if ((TO) == STACK_POINTER_REGNUM) \
{ \
(OFFSET) += current_function_outgoing_args_size; \
(OFFSET) += thumb_get_frame_size (); \
} \
}
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
if (TARGET_ARM) \
ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
else \
THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
#define INIT_EXPANDERS arm_init_expanders ()
#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
{ \
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
STATIC_CHAIN_REGNUM, PC_REGNUM); \
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
PC_REGNUM, PC_REGNUM); \
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
}
#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
{ \
fprintf (FILE, "\t.code 32\n"); \
fprintf (FILE, ".Ltrampoline_start:\n"); \
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
STATIC_CHAIN_REGNUM, PC_REGNUM); \
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
IP_REGNUM, PC_REGNUM); \
asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
IP_REGNUM, IP_REGNUM); \
asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
fprintf (FILE, "\t.word\t0\n"); \
fprintf (FILE, "\t.word\t0\n"); \
fprintf (FILE, "\t.code 16\n"); \
}
#define TRAMPOLINE_TEMPLATE(FILE) \
if (TARGET_ARM) \
ARM_TRAMPOLINE_TEMPLATE (FILE) \
else \
THUMB_TRAMPOLINE_TEMPLATE (FILE)
#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
#define TRAMPOLINE_ALIGNMENT 32
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
emit_move_insn \
(gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
emit_move_insn \
(gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
}
#define HAVE_POST_INCREMENT 1
#define HAVE_PRE_INCREMENT TARGET_ARM
#define HAVE_POST_DECREMENT TARGET_ARM
#define HAVE_PRE_DECREMENT TARGET_ARM
#define TEST_REGNO(R, TEST, VALUE) \
((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
(TEST_REGNO (REGNO, <, PC_REGNUM) \
|| TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
|| TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
(TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
|| (GET_MODE_SIZE (MODE) >= 4 \
&& TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
(TARGET_THUMB \
? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
: ARM_REGNO_OK_FOR_BASE_P (REGNO))
#define REGNO_OK_FOR_INDEX_P(REGNO) \
REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
#define MAX_REGS_PER_ADDRESS 2
#ifdef AOF_ASSEMBLER
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
#else
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == SYMBOL_REF \
&& (CONSTANT_POOL_ADDRESS_P (X) \
|| (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
#endif
#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
#define THUMB_LEGITIMATE_CONSTANT_P(X) \
( GET_CODE (X) == CONST_INT \
|| GET_CODE (X) == CONST_DOUBLE \
|| CONSTANT_ADDRESS_P (X) \
|| flag_pic)
#define LEGITIMATE_CONSTANT_P(X) \
(TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
#define SHORT_CALL_FLAG_CHAR '^'
#define LONG_CALL_FLAG_CHAR '#'
#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
(*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
(*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
#define SUBTARGET_NAME_ENCODING_LENGTHS
#endif
#define ARM_NAME_ENCODING_LENGTHS \
case SHORT_CALL_FLAG_CHAR: return 1; \
case LONG_CALL_FLAG_CHAR: return 1; \
case '*': return 1; \
SUBTARGET_NAME_ENCODING_LENGTHS
#undef ASM_OUTPUT_LABELREF
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
arm_asm_output_labelref (FILE, NAME)
#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
#ifndef REG_OK_STRICT
#define ARM_REG_OK_FOR_BASE_P(X) \
(REGNO (X) <= LAST_ARM_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| REGNO (X) == FRAME_POINTER_REGNUM \
|| REGNO (X) == ARG_POINTER_REGNUM)
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
(REGNO (X) <= LAST_LO_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| (GET_MODE_SIZE (MODE) >= 4 \
&& (REGNO (X) == STACK_POINTER_REGNUM \
|| (X) == hard_frame_pointer_rtx \
|| (X) == arg_pointer_rtx)))
#else
#define ARM_REG_OK_FOR_BASE_P(X) \
ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
#endif
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
(TARGET_THUMB \
? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
: ARM_REG_OK_FOR_BASE_P (X))
#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
#define REG_OK_FOR_INDEX_P(X) \
(TARGET_THUMB \
? THUMB_REG_OK_FOR_INDEX_P (X) \
: ARM_REG_OK_FOR_INDEX_P (X))
#define ARM_BASE_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
#define ARM_INDEX_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
#define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
do \
{ \
HOST_WIDE_INT range; \
enum rtx_code code = GET_CODE (INDEX); \
\
if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
{ \
if (code == CONST_INT && INTVAL (INDEX) < 1024 \
&& INTVAL (INDEX) > -1024 \
&& (INTVAL (INDEX) & 3) == 0) \
goto LABEL; \
} \
else \
{ \
if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
&& GET_MODE_SIZE (MODE) <= 4) \
goto LABEL; \
if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
&& (! arm_arch4 || (MODE) != HImode)) \
{ \
rtx xiop0 = XEXP (INDEX, 0); \
rtx xiop1 = XEXP (INDEX, 1); \
if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
&& power_of_two_operand (xiop1, SImode)) \
goto LABEL; \
if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
&& power_of_two_operand (xiop0, SImode)) \
goto LABEL; \
} \
if (GET_MODE_SIZE (MODE) <= 4 \
&& (code == LSHIFTRT || code == ASHIFTRT \
|| code == ASHIFT || code == ROTATERT) \
&& (! arm_arch4 || (MODE) != HImode)) \
{ \
rtx op = XEXP (INDEX, 1); \
if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
&& GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
&& INTVAL (op) <= 31) \
goto LABEL; \
} \
\
range = ((MODE) == HImode || (MODE) == QImode) \
? (arm_arch4 ? 256 : 4095) : 4096; \
if (code == CONST_INT && INTVAL (INDEX) < range \
&& INTVAL (INDEX) > -range) \
goto LABEL; \
} \
} \
while (0)
#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
{ \
if (ARM_BASE_REGISTER_RTX_P (X)) \
goto LABEL; \
else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
&& GET_CODE (XEXP (X, 0)) == REG \
&& ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
goto LABEL; \
else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
&& (GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == CONST \
&& GET_CODE (XEXP ((X), 0)) == PLUS \
&& GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
&& GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
goto LABEL; \
else if ((MODE) == TImode) \
; \
else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
{ \
if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT) \
{ \
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
if (val == 4 || val == -4 || val == -8) \
goto LABEL; \
} \
} \
else if (GET_CODE (X) == PLUS) \
{ \
rtx xop0 = XEXP (X, 0); \
rtx xop1 = XEXP (X, 1); \
\
if (ARM_BASE_REGISTER_RTX_P (xop0)) \
ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
} \
\
\
else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
&& GET_CODE (X) == SYMBOL_REF \
&& CONSTANT_POOL_ADDRESS_P (X) \
&& ! (flag_pic \
&& symbol_mentioned_p (get_pool_constant (X)))) \
goto LABEL; \
else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
&& (GET_MODE_SIZE (MODE) <= 4) \
&& GET_CODE (XEXP (X, 0)) == REG \
&& ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
goto LABEL; \
}
#define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
(GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
: GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
&& ((VAL) & 1) == 0) \
: ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
&& ((VAL) & 3) == 0))
#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
{ \
\
if (GET_MODE_SIZE (MODE) < 4 \
&& ! (reload_in_progress || reload_completed) \
&& ( reg_mentioned_p (frame_pointer_rtx, X) \
|| reg_mentioned_p (arg_pointer_rtx, X) \
|| reg_mentioned_p (virtual_incoming_args_rtx, X) \
|| reg_mentioned_p (virtual_outgoing_args_rtx, X) \
|| reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
|| reg_mentioned_p (virtual_stack_vars_rtx, X))) \
; \
\
else if (GET_CODE (X) == REG \
&& THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
goto WIN; \
\
else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
&& GET_CODE (X) == SYMBOL_REF \
&& CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
goto WIN; \
\
else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
&& (GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == CONST \
&& GET_CODE (XEXP (X, 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
goto WIN; \
\
else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
&& GET_CODE (XEXP (X, 0)) == REG \
&& THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
goto WIN; \
else if (GET_CODE (X) == PLUS) \
{ \
\
\
if (GET_MODE_SIZE (MODE) <= 4 \
&& GET_CODE (XEXP (X, 0)) == REG \
&& GET_CODE (XEXP (X, 1)) == REG \
&& XEXP (X, 0) != frame_pointer_rtx \
&& XEXP (X, 1) != frame_pointer_rtx \
&& XEXP (X, 0) != virtual_stack_vars_rtx \
&& XEXP (X, 1) != virtual_stack_vars_rtx \
&& THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
&& THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
goto WIN; \
\
else if (GET_CODE (XEXP (X, 0)) == REG \
&& (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
|| XEXP (X, 0) == arg_pointer_rtx) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
goto WIN; \
\
\
else if (GET_CODE (XEXP (X, 0)) == REG \
&& REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
&& GET_MODE_SIZE (MODE) >= 4 \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
+ GET_MODE_SIZE (MODE)) <= 1024 \
&& (INTVAL (XEXP (X, 1)) & 3) == 0) \
goto WIN; \
else if (GET_CODE (XEXP (X, 0)) == REG \
&& REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
&& GET_MODE_SIZE (MODE) >= 4 \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& (INTVAL (XEXP (X, 1)) & 3) == 0) \
goto WIN; \
} \
else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
&& GET_CODE (X) == SYMBOL_REF \
&& CONSTANT_POOL_ADDRESS_P (X) \
&& ! (flag_pic \
&& symbol_mentioned_p (get_pool_constant (X)))) \
goto WIN; \
}
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
if (TARGET_ARM) \
ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
else \
THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
{ \
if (GET_CODE (X) == PLUS) \
{ \
rtx xop0 = XEXP (X, 0); \
rtx xop1 = XEXP (X, 1); \
\
if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
xop0 = force_reg (SImode, xop0); \
if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
xop1 = force_reg (SImode, xop1); \
if (ARM_BASE_REGISTER_RTX_P (xop0) \
&& GET_CODE (xop1) == CONST_INT) \
{ \
HOST_WIDE_INT n, low_n; \
rtx base_reg, val; \
n = INTVAL (xop1); \
\
if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
{ \
low_n = n & 0x0f; \
n &= ~0x0f; \
if (low_n > 4) \
{ \
n += 16; \
low_n -= 16; \
} \
} \
else \
{ \
low_n = ((MODE) == TImode ? 0 \
: n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
n -= low_n; \
} \
base_reg = gen_reg_rtx (SImode); \
val = force_operand (gen_rtx_PLUS (SImode, xop0, \
GEN_INT (n)), NULL_RTX); \
emit_move_insn (base_reg, val); \
(X) = (low_n == 0 ? base_reg \
: gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
} \
else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
(X) = gen_rtx_PLUS (SImode, xop0, xop1); \
} \
else if (GET_CODE (X) == MINUS) \
{ \
rtx xop0 = XEXP (X, 0); \
rtx xop1 = XEXP (X, 1); \
\
if (CONSTANT_P (xop0)) \
xop0 = force_reg (SImode, xop0); \
if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
xop1 = force_reg (SImode, xop1); \
if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
(X) = gen_rtx_MINUS (SImode, xop0, xop1); \
} \
if (flag_pic) \
(X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
if (memory_address_p (MODE, X)) \
goto WIN; \
}
#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
if (flag_pic) \
(X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
if (TARGET_ARM) \
ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
else \
THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
{ \
if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
|| GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
goto LABEL; \
}
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
if (TARGET_ARM) \
ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
#define CASE_VECTOR_MODE Pmode
#ifndef DEFAULT_SIGNED_CHAR
#define DEFAULT_SIGNED_CHAR 0
#endif
#define NO_RECURSIVE_FUNCTION_CSE 1
#define MOVE_MAX 4
#undef MOVE_RATIO
#define MOVE_RATIO (arm_is_xscale ? 4 : 2)
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) \
(TARGET_THUMB ? ZERO_EXTEND : \
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
#define SLOW_BYTE_ACCESS 0
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define NO_FUNCTION_CSE 1
#define PROMOTE_PROTOTYPES 1
#define Pmode SImode
#define FUNCTION_MODE Pmode
#define ARM_FRAME_RTX(X) \
( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
|| (X) == arg_pointer_rtx)
#define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
return arm_rtx_costs (X, CODE, OUTER_CODE);
#define MEMORY_MOVE_COST(M, CLASS, IN) \
(TARGET_ARM ? 10 : \
((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
* (CLASS == LO_REGS ? 1 : 2)))
#define ARM_ADDRESS_COST(X) \
(10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
|| GET_CODE (X) == SYMBOL_REF) \
? 0 \
: ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
|| GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
? 10 \
: (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
: ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
|| GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
|| GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
|| GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
? 1 : 0)) \
: 4)))))
#define THUMB_ADDRESS_COST(X) \
((GET_CODE (X) == REG \
|| (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
&& GET_CODE (XEXP (X, 1)) == CONST_INT)) \
? 1 : 2)
#define ADDRESS_COST(X) \
(TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
#define BRANCH_COST \
(TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
extern int arm_pic_register;
extern const char * arm_pic_register_string;
#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
#define FINALIZE_PIC arm_finalize_pic (1)
#define LEGITIMATE_PIC_OPERAND_P(X) \
(!(symbol_mentioned_p (X) \
|| label_mentioned_p (X) \
|| (GET_CODE (X) == SYMBOL_REF \
&& CONSTANT_POOL_ADDRESS_P (X) \
&& (symbol_mentioned_p (get_pool_constant (X)) \
|| label_mentioned_p (get_pool_constant (X))))))
extern int making_const_table;
#define REGISTER_TARGET_PRAGMAS(PFILE) do { \
cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
} while (0)
#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
do \
{ \
if (GET_CODE (OP1) == CONST_INT \
&& ! (const_ok_for_arm (INTVAL (OP1)) \
|| (const_ok_for_arm (- INTVAL (OP1))))) \
{ \
rtx const_op = OP1; \
CODE = arm_canonicalize_comparison ((CODE), &const_op); \
OP1 = const_op; \
} \
} \
while (0)
#define STORE_FLAG_VALUE 1
#define MACHINE_DEPENDENT_REORG(INSN) \
arm_reorg (INSN); \
#undef ASM_APP_OFF
#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
#ifndef ASM_OUTPUT_INTERNAL_LABEL
#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
do \
{ \
char * s = (char *) alloca (40 + strlen (PREFIX)); \
\
if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
&& !strcmp (PREFIX, "L")) \
{ \
arm_ccfsm_state = 0; \
arm_target_insn = NULL; \
} \
ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
ASM_OUTPUT_LABEL (STREAM, s); \
} \
while (0)
#endif
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
if (TARGET_ARM) \
asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
STACK_POINTER_REGNUM, REGNO); \
else \
asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
if (TARGET_ARM) \
asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
STACK_POINTER_REGNUM, REGNO); \
else \
asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
#undef ASM_OUTPUT_CASE_LABEL
#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
do \
{ \
if (TARGET_THUMB) \
ASM_OUTPUT_ALIGN (FILE, 2); \
ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
} \
while (0)
#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
do \
{ \
if (TARGET_THUMB) \
{ \
if (is_called_in_ARM_mode (DECL)) \
fprintf (STREAM, "\t.code 32\n") ; \
else \
fprintf (STREAM, "\t.thumb_func\n") ; \
} \
if (TARGET_POKE_FUNCTION_NAME) \
arm_poke_function_name (STREAM, (char *) NAME); \
} \
while (0)
#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
do \
{ \
const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
\
if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
{ \
fprintf (FILE, "\t.thumb_set "); \
assemble_name (FILE, LABEL1); \
fprintf (FILE, ","); \
assemble_name (FILE, LABEL2); \
fprintf (FILE, "\n"); \
} \
else \
ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
} \
while (0)
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
if ((LOG) != 0) \
{ \
if ((MAX_SKIP) == 0) \
fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
else \
fprintf ((FILE), "\t.p2align %d,,%d\n", \
(LOG), (MAX_SKIP)); \
}
#endif
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
if (TARGET_ARM && optimize) \
arm_final_prescan_insn (INSN); \
else if (TARGET_THUMB) \
thumb_final_prescan_insn (INSN)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
(CODE == '@' || CODE == '|' \
|| (TARGET_ARM && (CODE == '?')) \
|| (TARGET_THUMB && (CODE == '_')))
#define PRINT_OPERAND(STREAM, X, CODE) \
arm_print_operand (STREAM, X, CODE)
#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
(HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
: ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
? ((~ (unsigned HOST_WIDE_INT) 0) \
& ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
: 0))))
#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
{ \
int is_minus = GET_CODE (X) == MINUS; \
\
if (GET_CODE (X) == REG) \
asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
else if (GET_CODE (X) == PLUS || is_minus) \
{ \
rtx base = XEXP (X, 0); \
rtx index = XEXP (X, 1); \
HOST_WIDE_INT offset = 0; \
if (GET_CODE (base) != REG) \
{ \
\
\
rtx temp = base; \
base = index; \
index = temp; \
} \
switch (GET_CODE (index)) \
{ \
case CONST_INT: \
offset = INTVAL (index); \
if (is_minus) \
offset = -offset; \
asm_fprintf (STREAM, "[%r, #%d]", \
REGNO (base), offset); \
break; \
\
case REG: \
asm_fprintf (STREAM, "[%r, %s%r]", \
REGNO (base), is_minus ? "-" : "", \
REGNO (index)); \
break; \
\
case MULT: \
case ASHIFTRT: \
case LSHIFTRT: \
case ASHIFT: \
case ROTATERT: \
{ \
asm_fprintf (STREAM, "[%r, %s%r", \
REGNO (base), is_minus ? "-" : "", \
REGNO (XEXP (index, 0))); \
arm_print_operand (STREAM, index, 'S'); \
fputs ("]", STREAM); \
break; \
} \
\
default: \
abort(); \
} \
} \
else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
|| GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
{ \
extern int output_memory_reference_mode; \
\
if (GET_CODE (XEXP (X, 0)) != REG) \
abort (); \
\
if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
asm_fprintf (STREAM, "[%r, #%s%d]!", \
REGNO (XEXP (X, 0)), \
GET_CODE (X) == PRE_DEC ? "-" : "", \
GET_MODE_SIZE (output_memory_reference_mode));\
else \
asm_fprintf (STREAM, "[%r], #%s%d", \
REGNO (XEXP (X, 0)), \
GET_CODE (X) == POST_DEC ? "-" : "", \
GET_MODE_SIZE (output_memory_reference_mode));\
} \
else output_addr_const (STREAM, X); \
}
#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
{ \
if (GET_CODE (X) == REG) \
asm_fprintf (STREAM, "[%r]", REGNO (X)); \
else if (GET_CODE (X) == POST_INC) \
asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
else if (GET_CODE (X) == PLUS) \
{ \
if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
asm_fprintf (STREAM, "[%r, #%d]", \
REGNO (XEXP (X, 0)), \
(int) INTVAL (XEXP (X, 1))); \
else \
asm_fprintf (STREAM, "[%r, %r]", \
REGNO (XEXP (X, 0)), \
REGNO (XEXP (X, 1))); \
} \
else \
output_addr_const (STREAM, X); \
}
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
if (TARGET_ARM) \
ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
else \
THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
#define RETURN_ADDR_RTX(COUNT, FRAME) \
arm_return_addr (COUNT, FRAME)
#define RETURN_ADDR_MASK26 (0x03fffffc)
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
#define MASK_RETURN_ADDR \
\
((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
: (arm_arch4 || TARGET_THUMB) ? \
(gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
: arm_gen_return_addr_mask ())
#define PREDICATE_CODES \
{"s_register_operand", {SUBREG, REG}}, \
{"arm_hard_register_operand", {REG}}, \
{"f_register_operand", {SUBREG, REG}}, \
{"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
{"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
{"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
{"index_operand", {SUBREG, REG, CONST_INT}}, \
{"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
{"offsettable_memory_operand", {MEM}}, \
{"bad_signed_byte_operand", {MEM}}, \
{"alignable_memory_operand", {MEM}}, \
{"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
{"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
{"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
{"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
{"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
{"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
{"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
{"load_multiple_operation", {PARALLEL}}, \
{"store_multiple_operation", {PARALLEL}}, \
{"equality_operator", {EQ, NE}}, \
{"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
LTU, UNORDERED, ORDERED, UNLT, UNLE, \
UNGE, UNGT}}, \
{"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
{"const_shift_operand", {CONST_INT}}, \
{"multi_register_push", {PARALLEL}}, \
{"cc_register", {REG}}, \
{"logical_binary_operator", {AND, IOR, XOR}}, \
{"dominant_cc_register", {REG}},
#define SPECIAL_MODE_PREDICATES \
"cc_register", "dominant_cc_register",
enum arm_builtins
{
ARM_BUILTIN_CLZ,
ARM_BUILTIN_MAX
};
#endif