#define TARGET_CPU_CPP_BUILTINS() \
do { \
builtin_assert("cpu=ia64"); \
builtin_assert("machine=ia64"); \
builtin_define("__ia64"); \
builtin_define("__ia64__"); \
builtin_define("__itanium__"); \
if (TARGET_BIG_ENDIAN) \
builtin_define("__BIG_ENDIAN__"); \
} while (0)
#define EXTRA_SPECS \
{ "asm_extra", ASM_EXTRA_SPEC },
#define CC1_SPEC "%(cc1_cpu) "
#define ASM_EXTRA_SPEC ""
extern int target_flags;
#define MASK_BIG_ENDIAN 0x00000001
#define MASK_GNU_AS 0x00000002
#define MASK_GNU_LD 0x00000004
#define MASK_NO_PIC 0x00000008
#define MASK_VOL_ASM_STOP 0x00000010
#define MASK_ILP32 0x00000020
#define MASK_B_STEP 0x00000040
#define MASK_REG_NAMES 0x00000080
#define MASK_NO_SDATA 0x00000100
#define MASK_CONST_GP 0x00000200
#define MASK_AUTO_PIC 0x00000400
#define MASK_INLINE_FLOAT_DIV_LAT 0x00000800
#define MASK_INLINE_FLOAT_DIV_THR 0x00001000
#define MASK_INLINE_INT_DIV_LAT 0x00002000
#define MASK_INLINE_INT_DIV_THR 0x00004000
#define MASK_INLINE_SQRT_LAT 0x00008000
#define MASK_INLINE_SQRT_THR 0x00010000
#define MASK_DWARF2_ASM 0x00020000
#define MASK_EARLY_STOP_BITS 0x00040000
#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
#define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
#define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
#define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
#define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
#define TARGET_ILP32 (target_flags & MASK_ILP32)
#define TARGET_B_STEP (target_flags & MASK_B_STEP)
#define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
#define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
#define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
#define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
#define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
#define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
#define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
#define TARGET_INLINE_FLOAT_DIV \
(target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
#define TARGET_INLINE_INT_DIV \
(target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
#define TARGET_INLINE_SQRT_LAT (target_flags & MASK_INLINE_SQRT_LAT)
#define TARGET_INLINE_SQRT_THR (target_flags & MASK_INLINE_SQRT_THR)
#define TARGET_INLINE_SQRT \
(target_flags & (MASK_INLINE_SQRT_LAT | MASK_INLINE_SQRT_THR))
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
#if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
#define TARGET_HAVE_TLS true
#endif
extern int ia64_tls_size;
#define TARGET_TLS14 (ia64_tls_size == 14)
#define TARGET_TLS22 (ia64_tls_size == 22)
#define TARGET_TLS64 (ia64_tls_size == 64)
#define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
#define TARGET_HPUX 0
#define TARGET_HPUX_LD 0
#ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
#define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
#endif
#define TARGET_SWITCHES \
{ \
{ "big-endian", MASK_BIG_ENDIAN, \
N_("Generate big endian code") }, \
{ "little-endian", -MASK_BIG_ENDIAN, \
N_("Generate little endian code") }, \
{ "gnu-as", MASK_GNU_AS, \
N_("Generate code for GNU as") }, \
{ "no-gnu-as", -MASK_GNU_AS, \
N_("Generate code for Intel as") }, \
{ "gnu-ld", MASK_GNU_LD, \
N_("Generate code for GNU ld") }, \
{ "no-gnu-ld", -MASK_GNU_LD, \
N_("Generate code for Intel ld") }, \
{ "no-pic", MASK_NO_PIC, \
N_("Generate code without GP reg") }, \
{ "volatile-asm-stop", MASK_VOL_ASM_STOP, \
N_("Emit stop bits before and after volatile extended asms") }, \
{ "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
N_("Don't emit stop bits before and after volatile extended asms") }, \
{ "b-step", MASK_B_STEP, \
N_("Emit code for Itanium (TM) processor B step")}, \
{ "register-names", MASK_REG_NAMES, \
N_("Use in/loc/out register names")}, \
{ "no-sdata", MASK_NO_SDATA, \
N_("Disable use of sdata/scommon/sbss")}, \
{ "sdata", -MASK_NO_SDATA, \
N_("Enable use of sdata/scommon/sbss")}, \
{ "constant-gp", MASK_CONST_GP, \
N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
N_("Generate self-relocatable code") }, \
{ "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
N_("Generate inline floating point division, optimize for latency") },\
{ "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
N_("Generate inline floating point division, optimize for throughput") },\
{ "no-inline-float-divide", \
-(MASK_INLINE_FLOAT_DIV_LAT|MASK_INLINE_FLOAT_DIV_THR), \
N_("Do not inline floating point division") }, \
{ "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
N_("Generate inline integer division, optimize for latency") }, \
{ "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
N_("Generate inline integer division, optimize for throughput") },\
{ "no-inline-int-divide", -(MASK_INLINE_INT_DIV_LAT|MASK_INLINE_INT_DIV_THR), \
N_("Do not inline integer division") }, \
{ "inline-sqrt-min-latency", MASK_INLINE_SQRT_LAT, \
N_("Generate inline square root, optimize for latency") }, \
{ "inline-sqrt-max-throughput", MASK_INLINE_SQRT_THR, \
N_("Generate inline square root, optimize for throughput") }, \
{ "no-inline-sqrt", -(MASK_INLINE_SQRT_LAT|MASK_INLINE_SQRT_THR), \
N_("Do not inline square root") }, \
{ "dwarf2-asm", MASK_DWARF2_ASM, \
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
N_("Disable Dwarf 2 line debug info via GNU as")}, \
{ "early-stop-bits", MASK_EARLY_STOP_BITS, \
N_("Enable earlier placing stop bits for better scheduling")}, \
{ "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
N_("Disable earlier placing stop bits")}, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
NULL } \
}
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_INLINE_FLOAT_DIV_THR)
#endif
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif
#ifndef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES
#endif
extern const char *ia64_fixed_range_string;
extern const char *ia64_tls_size_string;
enum processor_type
{
PROCESSOR_ITANIUM,
PROCESSOR_ITANIUM2,
PROCESSOR_max
};
extern enum processor_type ia64_tune;
extern const char *ia64_tune_string;
#define TARGET_OPTIONS \
{ \
{ "fixed-range=", &ia64_fixed_range_string, \
N_("Specify range of registers to make fixed"), 0}, \
{ "tls-size=", &ia64_tls_size_string, \
N_("Specify bit size of immediate TLS offsets"), 0}, \
{ "tune=", &ia64_tune_string, \
N_("Schedule code for given CPU"), 0}, \
}
#define OVERRIDE_OPTIONS ia64_override_options ()
#undef CC1_SPEC
#define CC1_SPEC "%{G*}"
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#if defined(__BIG_ENDIAN__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif
#define UNITS_PER_WORD 8
#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
do \
{ \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode; \
} \
while (0)
#define PARM_BOUNDARY 64
#define STACK_BOUNDARY 128
#ifndef IA64_STACK_ALIGN
#define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
#endif
#define FUNCTION_BOUNDARY 128
#define BIGGEST_ALIGNMENT 128
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#define STRICT_ALIGNMENT 1
#define PCC_BITFIELD_TYPE_MATTERS 1
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
#define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
#define TARGET_VTABLE_ENTRY_ALIGN 64
#define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
#define INT_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 96)
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
#define DEFAULT_SIGNED_CHAR 1
#define FIRST_PSEUDO_REGISTER 334
#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
#define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
#define GENERAL_REGNO_P(REGNO) \
(GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
#define GR_REG(REGNO) ((REGNO) + 0)
#define FR_REG(REGNO) ((REGNO) + 128)
#define PR_REG(REGNO) ((REGNO) + 256)
#define BR_REG(REGNO) ((REGNO) + 320)
#define OUT_REG(REGNO) ((REGNO) + 120)
#define IN_REG(REGNO) ((REGNO) + 112)
#define LOC_REG(REGNO) ((REGNO) + 32)
#define AR_CCV_REGNUM 329
#define AR_UNAT_REGNUM 330
#define AR_PFS_REGNUM 331
#define AR_LC_REGNUM 332
#define AR_EC_REGNUM 333
#define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
#define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
#define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
#define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
|| (REGNO) == AR_UNAT_REGNUM)
#define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
&& (REGNO) < FIRST_PSEUDO_REGISTER)
#define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
&& (REGNO) < FIRST_PSEUDO_REGISTER)
#define R_GR(REGNO) GR_REG (REGNO)
#define R_FR(REGNO) FR_REG (REGNO)
#define R_PR(REGNO) PR_REG (REGNO)
#define R_BR(REGNO) BR_REG (REGNO)
#define FIXED_REGISTERS \
{ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 1, 1, 1, 0, 1 \
}
#define CALL_USED_REGISTERS \
{ \
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 0, 0, 0, 0, 0, 1, 1, \
\
1, 1, 1, 1, 0, 1 \
}
#define CALL_REALLY_USED_REGISTERS \
{ \
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 0, 0, 0, 0, 0, 1, 1, \
\
0, 1, 0, 1, 0, 0 \
}
#define INCOMING_REGNO(OUT) \
((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
#define OUTGOING_REGNO(IN) \
((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
#define LOCAL_REGNO(REGNO) \
(IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
#define SELECT_CC_MODE(OP,X,Y) CCmode
#define REG_ALLOC_ORDER \
{ \
\
R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
R_GR (30), R_GR (31), \
\
R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
R_GR (126), R_GR (127), \
\
R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
\
R_GR (2), R_GR (3), \
\
R_FR (6), R_FR (7), \
\
R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
\
R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
R_FR (126), R_FR (127), \
\
R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
\
R_PR (16), R_PR (17), \
R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
\
R_BR (6), R_BR (7), \
\
\
R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
R_GR (108), \
\
R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
R_GR (118), R_GR (119), \
\
R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
\
R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
R_FR (30), R_FR (31), \
\
R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
\
R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
\
\
R_GR (109), R_GR (110), R_GR (111), \
\
\
R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
\
R_FR (0), R_FR (1), \
\
R_PR (0), \
\
R_BR (0), \
\
FRAME_POINTER_REGNUM, \
AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
AR_EC_REGNUM \
}
#define HARD_REGNO_NREGS(REGNO, MODE) \
((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(FR_REGNO_P (REGNO) ? \
GET_MODE_CLASS (MODE) != MODE_CC && \
(MODE) != TImode && \
(MODE) != BImode && \
(MODE) != TFmode \
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
: GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != XFmode \
: AR_REGNO_P (REGNO) ? (MODE) == DImode \
: BR_REGNO_P (REGNO) ? (MODE) == DImode \
: 0)
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
&& (((MODE1) == XFmode) == ((MODE2) == XFmode)) \
&& (((MODE1) == BImode) == ((MODE2) == BImode)))
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \
: choose_hard_reg_mode ((REGNO), (NREGS), false))
enum reg_class
{
NO_REGS,
PR_REGS,
BR_REGS,
AR_M_REGS,
AR_I_REGS,
ADDL_REGS,
GR_REGS,
FR_REGS,
GR_AND_BR_REGS,
GR_AND_FR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define GENERAL_REGS GR_REGS
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
#define REG_CLASS_NAMES \
{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
"ADDL_REGS", "GR_REGS", "FR_REGS", \
"GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
#define REG_CLASS_CONTENTS \
{ \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0000 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00FF }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0600 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x3800 }, \
\
{ 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0000 }, \
\
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0100 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x0000 }, \
\
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x01FF }, \
\
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x0100 }, \
\
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
}
#define REGNO_REG_CLASS(REGNO) \
(ADDL_REGNO_P (REGNO) ? ADDL_REGS \
: GENERAL_REGNO_P (REGNO) ? GR_REGS \
: FR_REGNO_P (REGNO) ? FR_REGS \
: PR_REGNO_P (REGNO) ? PR_REGS \
: BR_REGNO_P (REGNO) ? BR_REGS \
: AR_M_REGNO_P (REGNO) ? AR_M_REGS \
: AR_I_REGNO_P (REGNO) ? AR_I_REGS \
: NO_REGS)
#define BASE_REG_CLASS GENERAL_REGS
#define INDEX_REG_CLASS GENERAL_REGS
#define REG_CLASS_FROM_LETTER(CHAR) \
((CHAR) == 'f' ? FR_REGS \
: (CHAR) == 'a' ? ADDL_REGS \
: (CHAR) == 'b' ? BR_REGS \
: (CHAR) == 'c' ? PR_REGS \
: (CHAR) == 'd' ? AR_M_REGS \
: (CHAR) == 'e' ? AR_I_REGS \
: NO_REGS)
#define REGNO_OK_FOR_BASE_P(REGNO) \
(GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
(CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
: CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
: !OBJECT_P (X) \
&& (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
: CLASS)
#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
ia64_secondary_reload_class (CLASS, MODE, X)
#if 0
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
((MODE) == XFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
|| ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
#endif
#define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
: ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \
? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
#define CONST_OK_FOR_I(VALUE) \
((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
#define CONST_OK_FOR_J(VALUE) \
((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
#define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
#define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
#define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
#define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
#define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
#define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
: (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
: (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
: (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
: (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
: (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
: (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
: (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
: 0)
#define CONST_DOUBLE_OK_FOR_G(VALUE) \
((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
|| (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
#define CONSTRAINT_OK_FOR_Q(VALUE) \
(memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
#define CONSTRAINT_OK_FOR_R(VALUE) \
(GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
#define CONSTRAINT_OK_FOR_S(VALUE) \
(GET_CODE (VALUE) == MEM \
&& GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != RTX_AUTOINC \
&& (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
#define CONSTRAINT_OK_FOR_T(VALUE) \
(GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE))
#define EXTRA_CONSTRAINT(VALUE, C) \
((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
: (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
: (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
: (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE) \
: 0)
#define STACK_GROWS_DOWNWARD 1
#define STARTING_FRAME_OFFSET 0
#define STACK_POINTER_OFFSET 16
#define FIRST_PARM_OFFSET(FUNDECL) 0
#define RETURN_ADDR_RTX(COUNT, FRAME) \
ia64_return_addr_rtx (COUNT, FRAME)
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
#undef INCOMING_RETURN_ADDR_RTX
#define INCOMING_FRAME_SP_OFFSET 0
#define STACK_POINTER_REGNUM 12
#define FRAME_POINTER_REGNUM 328
#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
#define ARG_POINTER_REGNUM R_GR(0)
#define INIT_EXPANDERS \
do { \
if (cfun && cfun->emit->regno_pointer_align) \
REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
} while (0)
#define STATIC_CHAIN_REGNUM 15
#define FRAME_POINTER_REQUIRED 0
#define CAN_DEBUG_WITHOUT_FP
#define ELIMINABLE_REGS \
{ \
{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
}
#define CAN_ELIMINATE(FROM, TO) \
(TO == BR_REG (0) ? current_function_is_leaf : 1)
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
#define ACCUMULATE_OUTGOING_ARGS 1
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
#define MAX_ARGUMENT_SLOTS 8
#define MAX_INT_RETURN_SLOTS 4
#define GR_ARG_FIRST IN_REG (0)
#define GR_RET_FIRST GR_REG (8)
#define GR_RET_LAST GR_REG (11)
#define FR_ARG_FIRST FR_REG (8)
#define FR_RET_FIRST FR_REG (8)
#define FR_RET_LAST FR_REG (15)
#define AR_ARG_FIRST OUT_REG (0)
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
#define MUST_PASS_IN_STACK(MODE, TYPE) \
((TYPE) != 0 \
&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
|| TREE_ADDRESSABLE (TYPE)))
typedef struct ia64_args
{
int words;
int int_regs;
int fp_regs;
int prototype;
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
do { \
(CUM).words = 0; \
(CUM).int_regs = 0; \
(CUM).fp_regs = 0; \
(CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
} while (0)
#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
do { \
(CUM).words = 0; \
(CUM).int_regs = 0; \
(CUM).fp_regs = 0; \
(CUM).prototype = 1; \
} while (0)
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
(((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
: (((((MODE) == BLKmode \
? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
+ UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
? 128 : PARM_BOUNDARY)
#define FUNCTION_ARG_REGNO_P(REGNO) \
(((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
|| ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
#define EXPAND_BUILTIN_VA_ARG(valist, type) \
ia64_va_arg (valist, type)
#define FUNCTION_VALUE(VALTYPE, FUNC) \
ia64_function_value (VALTYPE, FUNC)
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG (MODE, \
(((GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
(MODE) != TFmode) \
? FR_RET_FIRST : GR_RET_FIRST))
#define FUNCTION_VALUE_REGNO_P(REGNO) \
(((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
|| ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
#define DEFAULT_PCC_STRUCT_RETURN 0
#define EXIT_IGNORE_STACK 1
#define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
#define EH_USES(REGNO) ia64_eh_uses (REGNO)
#define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
do { \
if ((PART) == 0) \
{ \
if (TARGET_ILP32) \
fputs ("\tdata8.ua @iplt(", FILE); \
else \
fputs ("\tdata16.ua @iplt(", FILE); \
mark_decl_referenced (DECL); \
assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
fputs (")\n", FILE); \
if (TARGET_ILP32) \
fputs ("\tdata8.ua 0\n", FILE); \
} \
} while (0)
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(FILE, LABELNO) \
do { \
char buf[20]; \
ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
if (TARGET_AUTO_PIC) \
fputs ("\tmovl out3 = @gprel(", FILE); \
else \
fputs ("\taddl out3 = @ltoff(", FILE); \
assemble_name (FILE, buf); \
if (TARGET_AUTO_PIC) \
fputs (");;\n", FILE); \
else \
fputs ("), r1;;\n", FILE); \
fputs ("\tmov out1 = r1\n", FILE); \
fputs ("\tmov out2 = b0\n", FILE); \
fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
} while (0)
#define STACK_SAVEAREA_MODE(LEVEL) \
((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
#define TRAMPOLINE_SIZE 32
#define TRAMPOLINE_ALIGNMENT 64
#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
#define TARGET_MEM_FUNCTIONS
#define HAVE_POST_INCREMENT 1
#define HAVE_POST_DECREMENT 1
#define HAVE_POST_MODIFY_DISP 1
#define HAVE_POST_MODIFY_REG 1
#define CONSTANT_ADDRESS_P(X) 0
#define MAX_REGS_PER_ADDRESS 2
#define LEGITIMATE_ADDRESS_REG(X) \
((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
|| (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
&& REG_OK_FOR_BASE_P (XEXP (X, 0))))
#define LEGITIMATE_ADDRESS_DISP(R, X) \
(GET_CODE (X) == PLUS \
&& rtx_equal_p (R, XEXP (X, 0)) \
&& (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
|| (GET_CODE (XEXP (X, 1)) == CONST_INT \
&& INTVAL (XEXP (X, 1)) >= -256 \
&& INTVAL (XEXP (X, 1)) < 256)))
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
do { \
if (LEGITIMATE_ADDRESS_REG (X)) \
goto LABEL; \
else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
&& LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
&& XEXP (X, 0) != arg_pointer_rtx) \
goto LABEL; \
else if (GET_CODE (X) == POST_MODIFY \
&& LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
&& XEXP (X, 0) != arg_pointer_rtx \
&& LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
goto LABEL; \
} while (0)
#ifdef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#else
#define REG_OK_FOR_BASE_P(X) \
(GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
#endif
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
goto LABEL;
#define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
|| GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
#define REGISTER_MOVE_COST ia64_register_move_cost
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
|| (CLASS) == GR_AND_FR_REGS ? 4 : 10)
#define BRANCH_COST 6
#define SLOW_BYTE_ACCESS 1
#define NO_FUNCTION_CSE
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
#define BSS_SECTION_ASM_OP "\t.bss"
#define IA64_DEFAULT_GVALUE 8
#define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
#define ASM_COMMENT_START "//"
#define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
#define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
extern int ia64_asm_output_label;
#define ASM_OUTPUT_LABEL(STREAM, NAME) \
do { \
ia64_asm_output_label = 1; \
assemble_name (STREAM, NAME); \
fputs (":\n", STREAM); \
ia64_asm_output_label = 0; \
} while (0)
#define GLOBAL_ASM_OP "\t.global "
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
ia64_asm_output_external (FILE, DECL, NAME)
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
do { \
sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
} while (0)
#define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
do { \
assemble_name (STREAM, NAME); \
fputs (" = ", STREAM); \
assemble_name (STREAM, VALUE); \
fputc ('\n', STREAM); \
} while (0)
#define REGISTER_NAMES \
{ \
\
"ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
"r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
"r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
"r30", "r31", \
\
"loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
"loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
"loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
"loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
"loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
"loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
"loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
"loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
"loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
"loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
\
"in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
\
"out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
\
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
"f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
"f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
"f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
"f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
"f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
"f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
"f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
"f120","f121","f122","f123","f124","f125","f126","f127", \
\
"p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
"p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
"p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
"p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
"p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
"p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
"p60", "p61", "p62", "p63", \
\
"b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
\
"sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
}
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "gp", R_GR (1) }, \
{ "sp", R_GR (12) }, \
{ "in0", IN_REG (0) }, \
{ "in1", IN_REG (1) }, \
{ "in2", IN_REG (2) }, \
{ "in3", IN_REG (3) }, \
{ "in4", IN_REG (4) }, \
{ "in5", IN_REG (5) }, \
{ "in6", IN_REG (6) }, \
{ "in7", IN_REG (7) }, \
{ "out0", OUT_REG (0) }, \
{ "out1", OUT_REG (1) }, \
{ "out2", OUT_REG (2) }, \
{ "out3", OUT_REG (3) }, \
{ "out4", OUT_REG (4) }, \
{ "out5", OUT_REG (5) }, \
{ "out6", OUT_REG (6) }, \
{ "out7", OUT_REG (7) }, \
{ "loc0", LOC_REG (0) }, \
{ "loc1", LOC_REG (1) }, \
{ "loc2", LOC_REG (2) }, \
{ "loc3", LOC_REG (3) }, \
{ "loc4", LOC_REG (4) }, \
{ "loc5", LOC_REG (5) }, \
{ "loc6", LOC_REG (6) }, \
{ "loc7", LOC_REG (7) }, \
{ "loc8", LOC_REG (8) }, \
{ "loc9", LOC_REG (9) }, \
{ "loc10", LOC_REG (10) }, \
{ "loc11", LOC_REG (11) }, \
{ "loc12", LOC_REG (12) }, \
{ "loc13", LOC_REG (13) }, \
{ "loc14", LOC_REG (14) }, \
{ "loc15", LOC_REG (15) }, \
{ "loc16", LOC_REG (16) }, \
{ "loc17", LOC_REG (17) }, \
{ "loc18", LOC_REG (18) }, \
{ "loc19", LOC_REG (19) }, \
{ "loc20", LOC_REG (20) }, \
{ "loc21", LOC_REG (21) }, \
{ "loc22", LOC_REG (22) }, \
{ "loc23", LOC_REG (23) }, \
{ "loc24", LOC_REG (24) }, \
{ "loc25", LOC_REG (25) }, \
{ "loc26", LOC_REG (26) }, \
{ "loc27", LOC_REG (27) }, \
{ "loc28", LOC_REG (28) }, \
{ "loc29", LOC_REG (29) }, \
{ "loc30", LOC_REG (30) }, \
{ "loc31", LOC_REG (31) }, \
{ "loc32", LOC_REG (32) }, \
{ "loc33", LOC_REG (33) }, \
{ "loc34", LOC_REG (34) }, \
{ "loc35", LOC_REG (35) }, \
{ "loc36", LOC_REG (36) }, \
{ "loc37", LOC_REG (37) }, \
{ "loc38", LOC_REG (38) }, \
{ "loc39", LOC_REG (39) }, \
{ "loc40", LOC_REG (40) }, \
{ "loc41", LOC_REG (41) }, \
{ "loc42", LOC_REG (42) }, \
{ "loc43", LOC_REG (43) }, \
{ "loc44", LOC_REG (44) }, \
{ "loc45", LOC_REG (45) }, \
{ "loc46", LOC_REG (46) }, \
{ "loc47", LOC_REG (47) }, \
{ "loc48", LOC_REG (48) }, \
{ "loc49", LOC_REG (49) }, \
{ "loc50", LOC_REG (50) }, \
{ "loc51", LOC_REG (51) }, \
{ "loc52", LOC_REG (52) }, \
{ "loc53", LOC_REG (53) }, \
{ "loc54", LOC_REG (54) }, \
{ "loc55", LOC_REG (55) }, \
{ "loc56", LOC_REG (56) }, \
{ "loc57", LOC_REG (57) }, \
{ "loc58", LOC_REG (58) }, \
{ "loc59", LOC_REG (59) }, \
{ "loc60", LOC_REG (60) }, \
{ "loc61", LOC_REG (61) }, \
{ "loc62", LOC_REG (62) }, \
{ "loc63", LOC_REG (63) }, \
{ "loc64", LOC_REG (64) }, \
{ "loc65", LOC_REG (65) }, \
{ "loc66", LOC_REG (66) }, \
{ "loc67", LOC_REG (67) }, \
{ "loc68", LOC_REG (68) }, \
{ "loc69", LOC_REG (69) }, \
{ "loc70", LOC_REG (70) }, \
{ "loc71", LOC_REG (71) }, \
{ "loc72", LOC_REG (72) }, \
{ "loc73", LOC_REG (73) }, \
{ "loc74", LOC_REG (74) }, \
{ "loc75", LOC_REG (75) }, \
{ "loc76", LOC_REG (76) }, \
{ "loc77", LOC_REG (77) }, \
{ "loc78", LOC_REG (78) }, \
{ "loc79", LOC_REG (79) }, \
}
#ifdef HAVE_AS_TLS
#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
ia64_output_dwarf_dtprel (FILE, SIZE, X)
#endif
#define PRINT_OPERAND(STREAM, X, CODE) \
ia64_print_operand (STREAM, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '+' || (CODE) == ',')
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
ia64_print_operand_address (STREAM, X)
#define REGISTER_PREFIX ""
#define LOCAL_LABEL_PREFIX "."
#define USER_LABEL_PREFIX ""
#define IMMEDIATE_PREFIX ""
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
if (TARGET_ILP32) \
fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
else \
fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
} while (0)
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
#define ADDR_VEC_ALIGN(ADDR_VEC) 3
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
(((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
| ((GLOBAL) ? DW_EH_PE_indirect : 0) \
| (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
do { \
const char *reltag = NULL; \
if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
reltag = "@segrel("; \
else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
reltag = "@gprel("; \
if (reltag) \
{ \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs (reltag, FILE); \
assemble_name (FILE, XSTR (ADDR, 0)); \
fputc (')', FILE); \
goto DONE; \
} \
} while (0)
#define ASM_NO_SKIP_IN_TEXT 1
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
do { \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs ("@secrel(", FILE); \
assemble_name (FILE, LABEL); \
fputc (')', FILE); \
} while (0)
#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
do { \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs ("@pcrel(", FILE); \
assemble_name (FILE, LABEL); \
fputc (')', FILE); \
} while (0)
#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
#define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
#define SYMBOL_REF_SMALL_ADDR_P(X) \
((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
#define PREDICATE_CODES \
{ "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
{ "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{ "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
{ "small_addr_symbolic_operand", {SYMBOL_REF}}, \
{ "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{ "function_operand", {SYMBOL_REF}}, \
{ "setjmp_operand", {SYMBOL_REF}}, \
{ "destination_operand", {SUBREG, REG, MEM}}, \
{ "not_postinc_memory_operand", {MEM}}, \
{ "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
SYMBOL_REF, CONST, LABEL_REF}}, \
{ "gr_register_operand", {SUBREG, REG}}, \
{ "fr_register_operand", {SUBREG, REG}}, \
{ "grfr_register_operand", {SUBREG, REG}}, \
{ "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
{ "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
{ "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
{ "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
{ "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT}}, \
{ "shift_count_operand", {SUBREG, REG, CONST_INT}}, \
{ "shift_32bit_count_operand", {SUBREG, REG, CONST_INT}}, \
{ "shladd_operand", {CONST_INT}}, \
{ "fetchadd_operand", {CONST_INT}}, \
{ "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{ "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
{ "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
{ "signed_inequality_operator", {GE, GT, LE, LT}}, \
{ "predicate_operator", {NE, EQ}}, \
{ "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
{ "ar_lc_reg_operand", {REG}}, \
{ "ar_ccv_reg_operand", {REG}}, \
{ "ar_pfs_reg_operand", {REG}}, \
{ "general_xfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
{ "destination_xfmode_operand", {SUBREG, REG, MEM}}, \
{ "xfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
{ "basereg_operand", {SUBREG, REG}},
#define CASE_VECTOR_MODE ptr_mode
#define CASE_VECTOR_PC_RELATIVE 1
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
#define MOVE_MAX 8
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define Pmode DImode
#define FUNCTION_MODE Pmode
#define SIMULTANEOUS_PREFETCHES 6
#define PREFETCH_BLOCK 32
#define HANDLE_SYSV_PRAGMA 1
#define MAX_CONDITIONAL_EXECUTE 12
extern int ia64_final_schedule;
#define IA64_UNWIND_INFO 1
#define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
struct machine_function GTY(())
{
rtx ia64_eh_epilogue_sp;
rtx ia64_eh_epilogue_bsp;
rtx ia64_gp_save;
int n_varargs;
};
enum ia64_builtins
{
IA64_BUILTIN_SYNCHRONIZE,
IA64_BUILTIN_FETCH_AND_ADD_SI,
IA64_BUILTIN_FETCH_AND_SUB_SI,
IA64_BUILTIN_FETCH_AND_OR_SI,
IA64_BUILTIN_FETCH_AND_AND_SI,
IA64_BUILTIN_FETCH_AND_XOR_SI,
IA64_BUILTIN_FETCH_AND_NAND_SI,
IA64_BUILTIN_ADD_AND_FETCH_SI,
IA64_BUILTIN_SUB_AND_FETCH_SI,
IA64_BUILTIN_OR_AND_FETCH_SI,
IA64_BUILTIN_AND_AND_FETCH_SI,
IA64_BUILTIN_XOR_AND_FETCH_SI,
IA64_BUILTIN_NAND_AND_FETCH_SI,
IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
IA64_BUILTIN_SYNCHRONIZE_SI,
IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
IA64_BUILTIN_LOCK_RELEASE_SI,
IA64_BUILTIN_FETCH_AND_ADD_DI,
IA64_BUILTIN_FETCH_AND_SUB_DI,
IA64_BUILTIN_FETCH_AND_OR_DI,
IA64_BUILTIN_FETCH_AND_AND_DI,
IA64_BUILTIN_FETCH_AND_XOR_DI,
IA64_BUILTIN_FETCH_AND_NAND_DI,
IA64_BUILTIN_ADD_AND_FETCH_DI,
IA64_BUILTIN_SUB_AND_FETCH_DI,
IA64_BUILTIN_OR_AND_FETCH_DI,
IA64_BUILTIN_AND_AND_FETCH_DI,
IA64_BUILTIN_XOR_AND_FETCH_DI,
IA64_BUILTIN_NAND_AND_FETCH_DI,
IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
IA64_BUILTIN_SYNCHRONIZE_DI,
IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
IA64_BUILTIN_LOCK_RELEASE_DI,
IA64_BUILTIN_BSP,
IA64_BUILTIN_FLUSHRS
};
enum fetchop_code {
IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
};
#define DONT_USE_BUILTIN_SETJMP
#undef PROFILE_BEFORE_PROLOGUE
#define PROFILE_BEFORE_PROLOGUE 1
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
#define CPU_UNITS_QUERY 1