MachineRegisterInfo.cpp [plain text]
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
VRegInfo.reserve(256);
RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); UsedPhysRegs.resize(TRI.getNumRegs());
PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
}
MachineRegisterInfo::~MachineRegisterInfo() {
#ifndef NDEBUG
for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
assert(!PhysRegUseDefLists[i] &&
"PhysRegUseDefLists has entries after all instructions are deleted");
#endif
delete [] PhysRegUseDefLists;
}
void
MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
unsigned VR = Reg;
Reg -= TargetRegisterInfo::FirstVirtualRegister;
assert(Reg < VRegInfo.size() && "Invalid vreg!");
const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
VRegInfo[Reg].first = RC;
std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
VRegs.erase(I);
RegClass2VRegMap[RC->getID()].push_back(VR);
}
unsigned
MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
assert(RegClass && "Cannot create register without RegClass!");
void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
HandleVRegListReallocation();
unsigned VR = getLastVirtReg();
RegClass2VRegMap[RegClass->getID()].push_back(VR);
return VR;
}
void MachineRegisterInfo::HandleVRegListReallocation() {
for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
MachineOperand *List = VRegInfo[i].second;
if (!List) continue;
List->Contents.Reg.Prev = &VRegInfo[i].second;
}
}
void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
assert(FromReg != ToReg && "Cannot replace a reg with itself");
for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
MachineOperand &O = I.getOperand();
++I;
O.setReg(ToReg);
}
}
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
"Invalid vreg!");
for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
if (I.getOperand().isDef())
return &*I;
}
return 0;
}
#ifndef NDEBUG
void MachineRegisterInfo::dumpUses(unsigned Reg) const {
for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
I.getOperand().getParent()->dump();
}
#endif